CYWUSB6935-48LFI

Manufacturer Part NumberCYWUSB6935-48LFI
DescriptionIC USB WIRELESS 2.4GHZ 48VQFN
ManufacturerCypress Semiconductor Corp
CYWUSB6935-48LFI datasheet
 


Specifications of CYWUSB6935-48LFI

Frequency2.4GHzData Rate - Maximum62.5kbps
Modulation Or ProtocolDSSS, GFSKApplicationsAMR, ISM, RKE
Power - Output0dBmSensitivity-95dBm
Voltage - Supply2.7 V ~ 3.6 VCurrent - Receiving57.7mA
Current - Transmitting69.1mAData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFNLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Memory Size-Other names428-1578
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WirelessUSB™ LR 2.4-GHz DSSS Radio SoC
1.0
Features
• 2.4-GHz radio transceiver
• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)
• –95-dBm receive sensitivity
• Up to 0dBm output power
• Range of up to 50 meters or more
• Data throughput of up to 62.5 kbits/sec
• Highly integrated low cost, minimal number of external
components required
• Dual DSSS reconfigurable baseband correlators
• SPI microcontroller interface (up to 2-MHz data rate)
• 13-MHz input clock operation
• Low standby current < 1 µA
• Integrated 32-bit Manufacturing ID
• Operating voltage from 2.7V to 3.6V
• Operating temperature from –40° to 85°C
• Offered in a small footprint 48 QFN or cost saving 28
SOIC
D IO V A L
D IO
IR Q
S S
S C K
D ig ita l
M IS O
M O S I
R E S E T
P D
Figure 3-1. CYWUSB6935 Simplified Block Diagram
Cypress Semiconductor Corporation
Document 38-16008 Rev. **
PRELIMINARY
2.0
The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct
Sequence Spread Spectrum (DSSS) Gaussian Frequency
Shift Keying (GFSK) baseband modem radio that connects
directly to a microcontroller.
The CYWUSB6935 is offered in an industrial temperature
range 48-pin QFN, 28-pin SOIC, and a commercial temper-
ature range 48-pin QFN.
3.0
• Building/Home Automation
— Climate Control
— Lighting Control
— Smart Appliances
— On-Site Paging Systems
— Alarm and Security
• Industrial Control
— Inventory Management
— Factory Automation
— Data Acquisition
• Automatic Meter Reading (AMR)
• Transportation
— Diagnostics
— Remote Keyless Entry
• Consumer / PC
— Locator Alarms
— Presenter Tools
— Remote Controls
— Toys
G F S K
D S S S
S E R D E S
M o d u la to r
B a s e b a n d
A
A
D S S S
S E R D E S
B a s e b a n d
G F S K
B
B
D e m o d u la to r
S y n th e s iz e r
3901 North First Street
CYWUSB6935
Functional Description
Applications
,
San Jose
CA 95134
Revised February 10, 2004
R F O U T
R F IN
408-943-2600

CYWUSB6935-48LFI Summary of contents

  • Page 1

    ... The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum (DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that connects directly to a microcontroller. The CYWUSB6935 is offered in an industrial temperature range 48-pin QFN, 28-pin SOIC, and a commercial temper- ature range 48-pin QFN. 3.0 • ...

  • Page 2

    ... The Radio Frequency (RF) circuitry has on-chip decoupling capacitors. The CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The CYWUSB6935 can be shutdown to a fully static state using the PD pin. CYWUSB6935 a data ...

  • Page 3

    ... Application Interfaces 5.1 SPI Interface The CYWUSB6935 has a four-wire SPI communication interface between an application MCU and one or more slave devices. The SPI interface supports single-byte and multi-byte serial transfers. The four-wire SPI communications interface consists of Master Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS) ...

  • Page 4

    ... Figure 5-1. SPI Transaction Format Figure 5-2. SPI Single Read Sequence Figure 5-3. SPI Burst Read Sequence addr data from Figure 5-4. SPI Single Write Sequence ata fro Figure 5-5. SPI Burst Write Sequence CYWUSB6935 Byte 1+N [7:0] Data from Page ...

  • Page 5

    ... Interrupts The CYWUSB6935 features three sets of interrupts: transmit, received, and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in transmit mode all receive interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes ...

  • Page 6

    ... ire 7.0 Register Descriptions Table 7-1 displays the list of registers inside the CYWUSB6935 that are addressable through the SPI interface. All registers are read and writable, except where noted. Table 7-1. CYWUSB6935 Register Map Register Name Revision ID Synthesizer A Counter Synthesizer N Counter ...

  • Page 7

    ... Table 7-1. CYWUSB6935 Register Map Register Name SERDES Control Receive Interrupt Enable Receive Interrupt Status Receive Data A Receive Valid A Receive Data B Receive Valid B Transmit Interrupt Enable Transmit Interrupt Status Transmit Data Transmit Valid PN Code Threshold Low Threshold High Wake Enable Wake Status ...

  • Page 8

    ... Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used to read the A and N values derived directly from the Channel. Document 38-16008 Rev. ** PRELIMINARY REG_ID Figure 7-1. Revision ID Register REG_SYN_A_CNT Figure 7-2. Synthesizer A Counter REG_SYN_N_CNT Count Figure 7-3. Synthesizer N Counter CYWUSB6935 Default: 0x07 Product ID Default: 0x00 Count Default: 0x00 Page ...

  • Page 9

    ... This bit only applies when Auto Syn Disable bit is selected (Reg 0x03, bit 1=1), otherwise this bit is don’t care. Document 38-16008 Rev. ** PRELIMINARY REG_CONTROL Auto Syn Auto PA Select Count Select Disable Figure 7-4. Control CYWUSB6935 Default: 0x00 Enable Auto Syn Syn Enable Disable Page ...

  • Page 10

    ... The following Reg 0x04, bits 2:0 values are not valid: • 001–Not Valid • 010–Not Valid • 011–Not Valid Document 38-16008 Rev. ** PRELIMINARY REG_DATA_RATE Figure 7-5. Data Rate CYWUSB6935 Default: 0x00 2 1 Code Width Data Rate Sample Rate Page ...

  • Page 11

    ... the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. Document 38-16008 Rev. ** PRELIMINARY REG_CONFIG Receive Invert Transmit Invert Figure 7-6. Configuration REG_SERDES_CTL SERDES Enable Figure 7-7. SERDES Control CYWUSB6935 Default: 0x01 Reserved IRQ Pin Select Default: 0x03 EOF Length Page ...

  • Page 12

    ... This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. Document 38-16008 Rev. ** PRELIMINARY REG_RX_INT_EN EOF B Full B Underflow A Figure 7-8. Receive Interrupt Enable CYWUSB6935 Default: 0x00 Overflow A EOF A Full A Page ...

  • Page 13

    ... TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These register are read-only. Document 38-16008 Rev. ** PRELIMINARY REG_RX_INT_STAT EOF B Full B Valid A Figure 7-9. Receive Interrupt Status CYWUSB6935 Default: 0x00 2 1 Flow Violation A EOF A [3] Page Full A ...

  • Page 14

    ... Document 38-16008 Rev. ** PRELIMINARY REG_RX_DATA_A Data Figure 7-10. Receive SERDES Data A REG_RX_VALID_A Valid Figure 7-11. Receive SERDES Valid A REG_RX_DATA_B Data Figure 7-12. Receive SERDES Data B REG_RX_VALID_B Valid Figure 7-13. Receive SERDES Valid B CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x00 Default: 0x00 Page ...

  • Page 15

    ... IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. Document 38-16008 Rev. ** PRELIMINARY REG_TX_INT_EN Underflow Figure 7-14. Transmit Interrupt Enable REG_TX_INT_STAT Underflow Figure 7-15. Transmit Interrupt Status CYWUSB6935 Default: 0x00 Overflow Done Empty Default: 0x00 Overflow Done Empty [4] ...

  • Page 16

    ... Transmit SERDES Valid register (Reg 0x10) will send half a byte. Document 38-16008 Rev. ** PRELIMINARY REG_TX_DATA Data Figure 7-16. Transmit SERDES Data REG_TX_VALID Valid Figure 7-17. Transmit SERDES Valid REG_PN_CODE Address 0x17 Address 0x16 Address 0x13 Address 0x12 Figure 7-18. PN Code CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x1E8B6A3DE0E9B222 Address 0x15 ...

  • Page 17

    ... Document 38-16008 Rev. ** PRELIMINARY REG_THRESHOLD_L Threshold Low Figure 7-19. Threshold Low REG_THRESHOLD_H Threshold High Figure 7-20. Threshold High CYWUSB6935 Default: 0x08 Default: 0x38 Page ...

  • Page 18

    ... No Device Reset. Document 38-16008 Rev. ** PRELIMINARY REG_WAKE_EN Reserved Figure 7-21. Wake Enable REG_WAKE_STAT Reserved Figure 7-22. Wake Status REG_ANALOG_CTL Reserved Reserved Enable Figure 7-23. Analog Control CYWUSB6935 Default: 0x00 Wakeup Enable Default: 0x01 Wakeup Status Default: 0x00 Output PaInv Rst Enable Page ...

  • Page 19

    ... The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). Document 38-16008 Rev. ** PRELIMINARY REG_CHANNEL Channel Figure 7-24. Channel REG_RSSI Valid REG_PA Figure 7-26. Power Control CYWUSB6935 Default: 0x00 Default: 0x00 RSSI [6] Default: 0x00 Bias Page ...

  • Page 20

    ... These bits are undefined for read operations. 5:0 Reserved These bits are reserved and should be written with zeros. Document 38-16008 Rev. ** PRELIMINARY REG_CRYSTAL_ADJ Crystal Adjust Figure 7-27. Crystal Adjust REG_VCO_CAL Reserved Figure 7-28. VCO Calibration CYWUSB6935 Default: 0x00 Default: 0x00 Page ...

  • Page 21

    ... Document 38-16008 Rev. ** PRELIMINARY REG_AGC_CTL Reserved Figure 7-29. AGC Control REG_CARRIER_DETECT Reserved Figure 7-30. Carrier Detect REG_CLOCK_MANUAL Manual Clock Overrides Figure 7-31. Clock Manual REG_CLOCK_ENABLE Manual Clock Enables Figure 7-32. Clock Enable CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x00 Default: 0x00 Page ...

  • Page 22

    ... The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only. Document 38-16008 Rev. ** PRELIMINARY REG_SYN_LOCK_CNT Count Figure 7-33. Synthesizer Lock Count REG_MID Address 0x3E Address 0x3D Figure 7-34. Manufacturing ID CYWUSB6935 Default: 0x64 ...

  • Page 23

    ... Master-Input-Slave-Output Data . SPI data output pin. /Hi-Z Input N/A SPI Input Clock . SPI clock. Input N/A Slave Select Enable . SPI enable 2.7V to 3.6V. CC VCC H Vcc = 2.7V to 3.6V. (Decouple separately from VCC pins) AVCC H Ground = 0V . GND L Tie to Ground. N/A N/A L Must be tied to Ground. GND CYWUSB6935 Description Page ...

  • Page 24

    ... RESET X13OUT 10 19 VCC SCK 11 18 DIOVAL MISO 12 17 DIO 13 16 MOSI 14 IRQ 15 SS Figure 8-1. CYWUSB6935, 28 SOIC – Top View CYWUSB6935 Top View CYWUSB6935 6 48 QFN Figure 8-2. CYWUSB6935, 48 QFN – Top View CYWUSB6935 X13IN 34 PACTL X13OUT 25 SCK Page ...

  • Page 25

    ... Ground Voltage ................................................................. 0V +0.3V F (Oscillator or Crystal Frequency) ..................... 13 MHz CC OSC 11.0 +0.3V CC Description Conditions < HIGH [11] no handshake [12] with handshaking CYWUSB6935 Operating Conditions DC Characteristics (over the operating range) [10] Min. Typ. 2.7 3.0 = –100.0µA V –0 –2.0 mA 2.4 3.0 = 2.0 mA 0.0 2.0 –0.3 < V –1 ...

  • Page 26

    ... SCK must start low, otherwise the success of SPI transactions are not guaranteed. Document 38-16008 Rev. ** PRELIMINARY Description fro Figure 12-1. SPI Timing Diagram t t SCK_LO SC K_HI (BU RST READ) every K_HI data DAT_VAL CYWUSB6935 Min. Typ. Max. Unit 476 ns 238 ns 158 ns 158 [15 [15] [15] 77 174 ns ...

  • Page 27

    ... Document 38-16008 Rev. ** PRELIMINARY Description Figure 12-3. DIO Receive Timing Diagram _IR _IR Q _LO data L_S L_H LD Figure 12-4. DIO Transmit Timing Diagram CYWUSB6935 Min. Typ. Max. 2.1 2 Min. Typ. Max. -0.01 6.1 -0.01 8.2 -0.01 16.1 -0.01 6.1 -0.01 8.2 -0 ...

  • Page 28

    ... C = –67 dBm C = –67 dBm [17 –67 dBm [17 –67 dBm C = –64 dBm ∆ 5,10 MHz seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 100-kHz resolution bandwidth, –6 dBc CYWUSB6935 Min. Typ. Max. Unit 2.400 2.483 GHz –3 ) –85 –95 dBm –20 –6 ...

  • Page 29

    ... A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0=1). Document 38-16008 Rev. ** PRELIMINARY [21] [22] [24] assert (wake interrupt) to within ±10 ppm Figure 12-5. Power On Reset/Reset Timing Figure 12-6. Sleep / Wake Timing CYWUSB6935 Conditions Min. Typ 2000 2.7V 1300 cc 1 1300 2000 10 50 2000 2100 ...

  • Page 30

    ... V 1 3.00 CC Figure 12-7. AC Test Loads and Waveforms for Digital Pins 13.0 Ordering Information Part Number Radio CYWUSB6935-28SEI Transceiver CYWUSB6935-48LFI Transceiver CYWUSB6935-48LFC Transceiver 14.0 Package Description 14 15 TOP VIEW 0.697[17.70] 0.713[18.11] 0.050[1.27] TYP. Figure 14-1. 28-pin (300-Mil) SOIC EPAD SE28.3 SOIC Document 38-16008 Rev ...

  • Page 31

    ... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Figure 14-2. 48-pin QFN LF48 CYWUSB6935 51-85152-*A Page ...

  • Page 32

    ... Document History Page Document Title: CYWUSB6935 WirelessUSB™ LR 2.4-GHz DSSS Radio SoC Document Number: 38-16008 REV. ECN NO. Issue Date ** 207428 See ECN Document 38-16008 Rev. ** PRELIMINARY Orig. of Change TGE New Data Sheet CYWUSB6935 Description of Change Page ...