XR18W750IL48-F Exar Corporation, XR18W750IL48-F Datasheet
XR18W750IL48-F
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XR18W750IL48-F Summary of contents
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MARCH 2008 GENERAL DESCRIPTION The XR18W750 is a Wireless UART Controller with a 2 two-wire I C interface to the XR18W753 RF transceiver to complete Exar’s Wireless UART chipset solution. The XR18W750 supports both the parallel and serial interfaces to ...
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... XR18W750 WIRELESS UART CONTROLLER IGURE IN UT SSIGNMENT MODEM_RESET GND CLK- CLK+ VCC TEST2 TEST1 RF_IRQ# RF_DO RF_DI SDA SCL ORDERING INFORMATION ART UMBER XR18W750IL48 48-Lead QFN XR18W750 ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. 1.0.0 36 EN_DIDO 35 TXRDY IOR# 25 VCC ANGE EVICE ...
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REV. 1.0.0 PIN DESCRIPTIONS Pin Description 48-QFN N T AME YPE PARALLEL MODE INTERFACE SIGNALS I ...
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XR18W750 WIRELESS UART CONTROLLER Pin Description 48-QFN N T AME YPE RTS CTS DTR DSR CD RI TRANSCEIVER INTERFACE SIGNALS MODEM_RESET 1 O RF_IRQ# ...
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REV. 1.0.0 Pin Description 48-QFN N T AME YPE CLK CLK GPIO[3:0] 13, 14, 15, I/O 48 TEST2 6 I TEST1 7 I TEST0 16 I VCC 5, 25 Pwr GND 2, 24 ...
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XR18W750 WIRELESS UART CONTROLLER 1.0 PRODUCT DESCRIPTION The XR18W750 is a Digital Baseband with a two-wire I complete Exar’s Wireless UART chipset solution. An external I proprietary firmware and Wireless UART chipset parameters. The XR18W750 is functionally, as well as ...
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REV. 1.0.0 1.4.1 XR18W753 RF Transceiver The XR18W753 Transceiver with frequency ranges of 868MHz - 954MHz and a data rate of 250kbps. All of the Physical Layer Management Entity (PLME) registers to configure and control the XR18W753 ...
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XR18W750 WIRELESS UART CONTROLLER 2.2 Point-to-Multipoint (Group Mode) Point-to-multipoint communication, also known as Group mode, is when one master station transmits a packet to all Wireless UART chipsets with the same Group ID. All Wireless UART chipsets with the same ...
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REV. 1.0.0 3.1.2 AT Commands The AT Commands supported are given in the table below. S YNTAX ATI3 Displays the firmware version. AT+PPM=[ Enable Point-to-Point Mode (P2P Enable Point-To-Multipoint Mode (P2M Enable Broadcast Mode ...
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XR18W750 WIRELESS UART CONTROLLER 3.2 Parallel Mode (CPU) Interface In the parallel mode, the CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The XR18W750 data interface ...
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REV. 1.0.0 3.3 Device Reset The RESET input resets the internal registers and the serial interface outputs to their default state (see Table 15). An active high pulse of longer than 40 ns duration will be required to activate the ...
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XR18W750 WIRELESS UART CONTROLLER 3.7 INT (IRQ#) Output The INT interrupt output changes according to the operating mode and enhanced features setup. and 5 summarize the operating behavior for the transmitter and receiver. When operating in the Motorola bus mode, ...
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REV. 1.0.0 The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit ...
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XR18W750 WIRELESS UART CONTROLLER 3.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and ...
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REV. 1.0 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Receive Data FIFO Receive Receive Data Byte and Errors N : Table-B selected as Trigger Table for ...
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XR18W750 WIRELESS UART CONTROLLER 3.13 Auto CTS Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature ...
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REV. 1.0.0 3.14 Internal Loopback The enhanced UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 10 shows ...
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XR18W750 WIRELESS UART CONTROLLER 4.0 UART INTERNAL REGISTERS The internal registers of the UART are selected by address lines A2-A0 in the parallel mode. In the serial mode, the UART registers are not accessible via these address lines. The 8051 ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD AME RITE RHR RD Bit THR WR Bit ...
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XR18W750 WIRELESS UART CONTROLLER T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD AME RITE DLL RD/WR Bit DLM RD/WR Bit-7 0 ...
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REV. 1.0.0 5.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the ...
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XR18W750 WIRELESS UART CONTROLLER IER[5]: Reserved For normal operation, this bit should be ’0’. IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The ...
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REV. 1.0.0 ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic interrupt pending (default condition). ISR[3:1]: Interrupt ...
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XR18W750 WIRELESS UART CONTROLLER FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level ...
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REV. 1.0.0 T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table 5.6 Line Control Register (LCR) ...
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XR18W750 WIRELESS UART CONTROLLER LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 11 for parity selection ...
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REV. 1.0.0 MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • Logic 0 = Force DTR# output HIGH (default). • ...
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XR18W750 WIRELESS UART CONTROLLER LSR[4]: Receive Break Error Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO ...
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REV. 1.0.0 MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be ...
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XR18W750 WIRELESS UART CONTROLLER EMSR[1:0]: Receive/Transmit FIFO Level Count (Write-Only) When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in. T FCTR[6] EMSR[1] EMSR[0] Scratchpad ...
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REV. 1.0.0 EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (for 16C550 compatibility, default). LSR bits 2, 3, and 4 will generate an interrupt when the character with the error is in the RHR. • Logic 1 ...
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XR18W750 WIRELESS UART CONTROLLER FCTR[3:2]: Reserved For normal operation, these bits should be ’0’. FCTR[5:4]: Transmit/Receive Trigger Table Select See Table 10 for more details. FCTR FCTR[6]: Scratchpad Swap • Logic 0 = ...
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REV. 1.0.0 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled ...
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XR18W750 WIRELESS UART CONTROLLER REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. RHR Bits 7-0 = 0xXX THR Bits ...
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REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-QFN) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA (-40 +85 ...
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XR18W750 WIRELESS UART CONTROLLER AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 3.63V LOAD WHERE APPLICABLE S P YMBOL ARAMETER ECLK External Clock (CMOS/TTL or Differential) T Address Setup Time (16 mode Address ...
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REV. 1.0.0 AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 3.63V LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Delay From Initial INT Reset To Transmit Start INT T Delay From IOW# To Reset Interrupt ...
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XR18W750 WIRELESS UART CONTROLLER F 12 IGURE ODE NTEL ATA A0-A2 Valid Address CS IOR# T RDV D0- IGURE ODE NTEL ATA A0-A2 ...
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REV. 1.0 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# ...
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XR18W750 WIRELESS UART CONTROLLER F 16 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
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XR18W750 WIRELESS UART CONTROLLER F 20 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY ...
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REV. 1.0.0 PACKAGE DIMENSIONS (48 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL WIRELESS UART CONTROLLER ) mm INCHES MILLIMETERS MIN MAX MIN 0.031 ...
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... Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...