XR18W750IL48-F Exar Corporation, XR18W750IL48-F Datasheet - Page 20

• Manufacturer Part Number: XR18W750IL48-F
• Description: IC WIRELESS UART CTRLR 48QFN
• Manufacturer: Exar Corporation

Specifications of XR18W750IL48-F

• Package / Case: 48-VFQFN Exposed Pad
• Function: Controller
• Rf Type: General Purpose
• Secondary Attributes: I²C Interface
• Processor Series: XR18W750
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 400 KHz
• Number Of Timers: 1
• Operating Supply Voltage: 2.25 V to 3.63 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: XR18W750/753-0A-EB, XR18W750/753-0B-EB
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR18W750
WIRELESS UART CONTROLLER
SEE”RECEIVER” ON PAGE 14.
SEE”TRANSMITTER” ON PAGE 12.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
A2 A1 A0
5.0 INTERNAL REGISTER DESCRIPTIONS
5.1
5.2
5.3
A
1 X X
0 0 0
0 0 1
0 0 0
0 0 1
0 0 0
0 0 0
0 0 1
0 1 0
DDRESS
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
DREV
FCTR RD/WR
Rsrvd RD/WR
N
DVID
DLM
TRG
EFR
R
DLL
FC
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR
RD/WR
R
W
WR
RD
RD
RD
EAD
RITE
/
Enable
RX/TX
Mode
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Auto
CTS
Bit-7
IT
0
-7
SCPAD
Enable
Swap
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Auto
Bit-6
RTS
IT
0
-6
Baud Rate Generator Divisor
Enhanced Registers
Rsrvd
Table
B
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-1
Bit-5
Trig
IT
0
-5
20
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Enable
B
Table
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-4
Trig
IT
0
-4
S
HADED BITS ARE ENABLED WHEN
Rsrvd
Rsrvd
B
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
IT
1
-3
Rsrvd
Rsrvd
B
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
IT
0
-2
Rsrvd
B
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Auto
Hyst
Bit-1
Bit-1
RTS
IT
1
-1
EFR B
Rsrvd
B
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Auto
Bit-0
Bit-0
RTS
Hyst
IT
0
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
DLM=0x00
DLL=0x00
C
LCR[7]=1
LCR[7]=1
REV. 1.0.0
OMMENT
X
BF