XRT94L31IB Exar Corporation, XRT94L31IB Datasheet

no-image

XRT94L31IB

Manufacturer Part Number
XRT94L31IB
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT94L31IB

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L31IB
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT94L31IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT94L31IB-L
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
XRT94L31IB-L
Quantity:
355
MARCH 2007
GENERAL DESCRIPTION
The XRT94L31 is a highly integrated SONET/SDH
terminator designed for E3/DS3/STS-1 mapping/de-
mapping functions from either the STS-3 or STM-1
data stream. The XRT94L31 interfaces directly to the
optical transceiver.
The XRT94L31 processes the section, line and path
overhead in the SONET/SDH data stream. The
processing of path overhead bytes within the STS-1s
or TUG-3s includes 64 bytes for storing the J1 bytes.
Path overhead bytes can be accessed through the
microprocessor interface or via serial interface.
The XRT94L31 uses the internal E3/DS3 De-
Synchronizer circuit with an internal pointer leak
algorithm for clock smoothing as well as to remove
the jitter due to mapping and pointer movements.
These De-Synchronizer circuits do not need any
external clock reference for its operation.
The SONET/SDH transmit blocks allow flexible
insertion of TOH and POH bytes through both
Hardware and Software. Individual POH bytes for the
transmitted SONET/SDH signal are mapped either
from the XRT94L31 memory map or from external
interface. A1, A2 framing pattern, C1 byte and H1, H2
pointer byte are generated.
The SONET/SDH receive blocks receive SONET
STS-3 signal or SDH STM-1 signal and perform the
necessary transport and path overhead processing.
The XRT94L31 provides a line side APS (Automatic
Protection Switching) interface by offering redundant
receive serial interface to be switched at the frame
boundary.
The XRT94L31 provides 3 mappers for performing
STS-1/VC-3 to STS-1/DS3/E3 mapping function, one
for each STS-1/DS3/E3 framers.
A PRBS test pattern generation and detection is
implemented to measure the bit-error performance.
A
included for control, configuration and monitoring.
Exar
general-purpose
Corporation 48720 Kato Road, Fremont CA, 94538
microprocessor
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
interface
is
(510) 668-7000
APPLICATIONS
FEATURES
Network switches
Add/Drop Multiplexer
W-DCS Digital Cross Connect Systems
Provides DS3/ E3 mapping/de-mapping for up to 3
tributaries through SONET STS-1 or SDH AU-3
and/or TUG-3/AU-4 containers
Generates and terminates SONET/SDH section,
line and path layers
Integrated SERDES with Clock Recovery Circuit
Provides
descrambling
Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external 12.96/
19.44/77.76 MHz reference clock
Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit
that de-jitter gapped clock to meet 0.05UIpp jitter
requirements
Access to Line or Section DCC
Level 2 Performance Monitoring for E3 and DS3
Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
E3 and DS3 framers for both Transmit and Receive
directions
Complete Transport/Section Overhead Processing
and generation per Telcordia and ITU standards
Single PHY and Multi-PHY operations supported
Full line APS support for redundancy applications
Loopback support for both SONET/SDH as well as
E3/DS3/STS-1
Boundary scan capability with JTAG IEEE 1149·8-
bit microprocessor interface·
3.3 V ± 5% Power Supply; 5 V input signal
tolerance
-40°C to +85°C Operating Temperature Range
Available in a 504 Ball TBGA package
FAX (510) 668-7017
SONET
frame
XRT94L31
www.exar.com
scrambling
REV. 1.0.1
and

Related parts for XRT94L31IB

XRT94L31IB Summary of contents

Page 1

MARCH 2007 GENERAL DESCRIPTION The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/de- mapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the optical transceiver. The XRT94L31 processes the section, line ...

Page 2

... Block Tx STS-1 Tx STS-1 Tx STS-1 Tx STS-1 TOH TOH TOH TOH Processor Processor Processor Processor Block Block Block Block ORDERING INFORMATION PART NUMBER XRT94L31IB XRT94L31 Rx STS-1 Rx STS-1 Rx STS-1 Rx STS-1 POH POH POH POH Processor Processor Processor Processor Block Block Block Block Tx SONET Tx SONET ...

Page 3

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O Y22 PCLK I AD25 PTYPE_0PTYPE_1P I AD23 TYPE_2 AC21 AD27 PADDR_0 I AB25 PADDR_1 W23 PADDR_2 Y24 PADDR_3 AD26 PADDR_4 AC25 PADDR_5 AA24 PADDR_6 Y23 PADDR_7 ...

Page 4

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AD20 PDATA_0 I/O AC19 PDATA_1 AE22 PDATA_2 AG24 PDATA_3 AE21 PDATA_4 AD19 PDATA_5 AF23 PDATA_6 AE20 PDATA_7 AF22 PWR_L/R/W* I TYPE ...

Page 5

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AC18 PRD_L/DS*/WE* I AG23 ALE/AS_L I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL READ Strobe /Data Strobe: The function of this input pin depends ...

Page 6

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AE19 PCS_L I AD18 PRDY_L/ O DTACK*RDY TYPE DESCRIPTION TTL Chip Select Input: This active-low signal must be asserted in order ...

Page 7

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AF21 PDBEN_L I AF20 PBLAST_L I AG22 PINT_L O AB24 RESET_L I AE18 DIRECT_ADD_SEL I SONET/SDH SERIAL LINE INTERFACE PINS T3 RXLDAT_P I T2 RXLDAT_N I ...

Page 8

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O U2 RXLDAT_R_P I U1 RXLDAT_R_N I AE27 RXCLK_19MHZ O P3 REFCLK_P I P2 REFCLK_N I TYPE DESCRIPTION LVPEC Receive STS-3/STM-1 Data ...

Page 9

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O P5 TXLDATO_P O P6 TXLDATO_N O M4 TXLDATO_R_P O M3 TXLDATO_R_N O 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION LVPEC Transmit STS-3/STM-1 Data - Positive ...

Page 10

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O N6 TXLCLKO_P O N5 TXLCLKO_N O M1 TXLCLKO_R_P O M2 TXLCLKO_R_N O TYPE DESCRIPTION LVPEC Transmit STS-3/STM-1 Clock - Positive Polarity ...

Page 11

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O P1 REFTTL I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL 19.44MHz or 77.76MHz Clock Synthesizer Reference Clock Input Pin: The function of this input ...

Page 12

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG3 LOSTTL I TYPE DESCRIPTION TTL Loss of Optical Carrier Input - Primary Receive STS-3/STM-1 PECL Interface - TTL Input: If ...

Page 13

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG25 LOSTTL_R I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Loss of Optical Carrier Input - Redundant Receive STS-3/STM-1 PECL Interface - TTL Input: ...

Page 14

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O L4 LOSPECL_P I TYPE DESCRIPTION LVPEC Loss of Optical Carrier/Signal Input - Single-Ended PECL Interface L Input - Primary Receive STS-3/STM-1 ...

Page 15

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O L3 LOSPECL_R I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION LVPEC Loss of Optical Carrier/Signal Input - Single-Ended PECL Interface L Input - Redundant Receive ...

Page 16

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O V1 LOCKDET O STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION E1 TXA_CLK O F2 TXA_C1J1whether or O not the TYPE DESCRIPTION ...

Page 17

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E2 TXA_ALARM O H3 TXA_DP O G4 TxSBFP I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Transmit STS-3/STM-1 Telecom Bus - Alarm Indicator Output ...

Page 18

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O K5 TxA_PL O J4 TxA_D0 O G3 TxA_D1 D1 TxA_D2 F3 TxA_D3 J5 TxA_D4 H4 TxA_D5 D2 TxA_D6 E3 TxA_D7 STS-3/STM-1 ...

Page 19

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AD1 RxD_C1J1 I AB3 RxD_DP I W1 RxD_ALARM I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Receive STS-3/STM-1 Telecom Bus Interface - C1/J1 Byte ...

Page 20

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O Y2 RxD_D0 I AD2 RxD_D1 AC3 RxD_D2 AA4A RxD_D3 B4 RxD_D4 Y1 RxD_D5 AD3 RxD_D6 AA5 RxD_D7 SONET/SDH OVERHEAD INTERFACE - ...

Page 21

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O F8 TxTOH I E8 TxTOHFrame O 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Transmit TOH Input Port - Input pin: This input pin, along ...

Page 22

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D6 TxTOHIns I B4 TxLDCCEnable O TYPE DESCRIPTION TTL Transmit TOH Input Port - Insert Enable Input pin: This input pin, ...

Page 23

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D7 TxSDCCEnable O C5 TxSDCC I D8 TxLDCC I 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Transmit - Section DCC Input Port - Enable ...

Page 24

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E9 TxE1F1E2Enable O C6 TxE1F1E2Frame O A4 TxE1F1E2 I TYPE DESCRIPTION CMOS Transmit E1-F1-E2 Byte Input Port - Enable (or Ready) ...

Page 25

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C7 TXPOH I D9 TXPOHCLK O B5 TXPOHFRAME O 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Transmit Path Overhead Input Port - Input pin. ...

Page 26

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C8 TXPOHINS I B6 TXPOHENABLE O E10 TxPOH_0 I B8 TxPOH_1 D11 TxPOH_2 TYPE DESCRIPTION TTL Transmit Path Overhead Input Port ...

Page 27

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A5 TxPOHClk_0 O A6 TxPOHClk_1 A7 TxPOHClk_2 C9 TxPOHFrame_0 O C10 TxPOHFrame_1 A8 TxPOHFrame_2 D10 TxPOHIns_0 I E11 TxPOHIns_1 C11 TxPOHIns_2 B7 TxPOHEnable_0 O B9 TxPOHEnable_1 ...

Page 28

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C12 TXDS3CLK_0 I TXE3CLK_0 B20 TXDS3CLK_1 TXE3CLK_1 AF17 TXDS3CLK_2 TXE3CLK_2 B11 TxOHClk_0 O A22 TxOHClk_1 AD16 TxOHClk_2 TYPE DESCRIPTION TTL Transmit ...

Page 29

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D12 TxOHENABLE_0 O C18 TxOHENABLE_1 AC16 TxOHENABLE_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Transmit Overhead Enable Output indicator This output pin functions as ...

Page 30

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E12 TxOH_0 I E17 TxOH_1 AB16 TxOH_2 TYPE DESCRIPTION TTL Transmit Overhead Data Input: This input pin functions as the Transmit ...

Page 31

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E12 TxOH_0 I E17 TxOH_1 AB16 TxOH_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Continued If the user is inserting both POH and TOH ...

Page 32

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O F12 TxOHINS_0 I B19 TxOHINS_1 AG19 TxOHINS_2 TYPE DESCRIPTION TTL Transmit Overhead Data Insert Input: This input pin functions as the ...

Page 33

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A9 TxOHFRAME_0 O D17 TxOHFRAME_1 AF18 TxOHFRAME_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Transmit Overhead Framing Pulse: This input pin functions as the ...

Page 34

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AF19 STUFFCNTL_0/ I/O TXHDLC_CLK_0 AG21 STUFFCNTL_1/ TXHDLC_CLK_1 AE17 STUFFCNTL_2/ TXHDLC_CLK_2 AC17 EIGHTKHZSYNC_0/ I/O RXHDLC_CLK_0 AD17 EIGHTKHZSYNC_1/ RXHDLC_CLK_1 AG20 EIGHTKHZSYNC_2/ RXHDLC_CLK_2 D27 ...

Page 35

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O F25 TxMOD_0 I J24 TxUPRTY/TxPPRTY I H27 TxUDATA_0/ I TxPDATA_0 G27 TxUDATA_1/ TxPDATA_1 L24 TxUDATA_2/ TxPDATA_2 J26 TxUDATA_3/ TxPDATA_3 L23 TxUDATA_4/ TxPDATA_4 K25 TxUDATA_5/ TxPDATA_5 F27 ...

Page 36

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O M27 TXUCLK/TXPCLK I STS-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION C14 STS1TXA_CK_0 I TXSENDFCS_0 I TXGFCCLK_0 O E19 STS1TXA_CK_1 TXSENDFCS_1 TXGFCCLK_1 ...

Page 37

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E14 STS1TXA_PL_0 I TXSENDMSG_0 c22 STS1TXA_PL_n TXSENDMSG_n AD14 STS1TXA_PL_n TXSENDMSG_n 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL STS-1 Transmit Telecom Bus - Payload Indicator ...

Page 38

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D14 STS1TXA_C1J1_0RX I DS3LINECLK_0 STS1TXA_C1J1_nRX A24 DS3LINECLK_n STS1TXA_C1J1_nRX AF14 DS3LINECLK_n TYPE DESCRIPTION TTL STS-1 Transmit Telecom Bus C1/J1 Byte Phase Indicator ...

Page 39

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B14 STS1TXA_DP_n I RXDS3POS_n C21 STS1TXA_DP_n RXDS3POS_n AG15 STS1TXA_DP_n RXDS3POS_n 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL STS-1 Transmit Telecom Bus - Parity Input ...

Page 40

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A13 STS1TXA_ALARM_n I RXDS3NEG_n RxLCV_n D19 STS1TXA_ALARM_n RXDS3NEG_n RxLCV_n AF15 STS1TXA_ALARM_n RXDS3NEG_n RxLCV_n TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus - ...

Page 41

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B13 STS1TXA_0_D0 I/O TXHDLCDAT_0_0 TXGFCMSB_0 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input ...

Page 42

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C13 STS1TXA_0_D1 I TXHDLCDAT_0_1 TXGFC_0 TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input pin ...

Page 43

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D13 STS1TXA_0_D2 I TXHDLCDAT_0_2 TXCELLTXED_0 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input ...

Page 44

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E13 STS1TXA_0_D3 I/O TXHDLCDAT_0_3 SSI_CLK TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input CMOS ...

Page 45

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E13 STS1TXA_0_D3 I/O TXHDLCDAT_0_3 SSI_CLK(Continued) 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input ...

Page 46

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A12 STS1TXA_0_D4 IO TXHDLCDAT_0_4 TXDS3OHIND_0 TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input CMOS ...

Page 47

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A12 STS1TXA_0_D4 I/O TXHDLCDAT_0_4 TXDS3OHIND_0(Con tinued) 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus - Channel 0 - Input Data Bus ...

Page 48

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A11 STS1TXA_0_D5TXH I/O DLCDAT_0_5TXDS3 FP_0 TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 0 - Input Data Bus CMOS ...

Page 49

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B12 STS1TXA_0_D6 I TXHDLCDAT_0_6 TXDS3DATA_0 TXSBDATA_6_0 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus ...

Page 50

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A10 STS1TXA_D7_0 I TXHDLCDAT_7_0 TXAISEN_0 TXSBDATA_7_0 TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 0 - Input Data Bus ...

Page 51

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B23 STS1TXA_1_D0 I/O TXHDLCDAT_1_0 TXGFCMSB_1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus ...

Page 52

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C20 STS1TXA_1_D1 I TXHDLCDAT_1_1 TXGFC_1 TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input pin ...

Page 53

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B22 STS1TXA_1_D2 I/O TXHDLCDAT_1_2 TXCELLTXED_1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input ...

Page 54

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O E18 STS1TXA_1_D3 I/O TXHDLCDAT_1_3 SSI_POS TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input CMOS ...

Page 55

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A23 STS1TXA_1_D4 I/O TXHDLCDAT_1_4 TXDS3OHIND_1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus ...

Page 56

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C19 STS1TXA_1_D5 I/O TXHDLCDAT_1_5 TXDS3FP_1 TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus CMOS ...

Page 57

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D18 STS1TXA_1_D6 I TXHDLCDAT_1_6 TXDS3DATA_1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input ...

Page 58

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B21 STS1TXA_1_D7TXH I DLCDAT_1_7TXAISE N_1 TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus pin ...

Page 59

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AE15 STS1TXA_2_D0 I/O TXHDLCDAT_2_0 TXGFCMSB_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Input Data Bus ...

Page 60

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AD15 STS1TXA_2_D1 I TXHDLCDAT_2_1 TXGFC_2 TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input pin ...

Page 61

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AC15 STS1TXA_2_D2 I/O TXHDLCDAT_2_2 TXCELLTXED_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input ...

Page 62

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG16 STS1TXA_2_D3 I/O TXHDLCDAT_2_3 SSI_NEG TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input CMOS ...

Page 63

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG17 STS1TXA_2_D4 I/O TXHDLCDAT_2_4 TXDS3OHIND_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input ...

Page 64

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AF16 STS1TXA_2_D5 I/O TXHDLCDAT_2_5 TXDS3FP_2 TYPE DESCRIPTION TTL/ Transmit STS-1 Telecom Bus Interface - Channel 2 - Input Data Bus pin ...

Page 65

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG18 STS1TXA_2_D6TXH I DLCDAT_2_6TXDS3 DATA_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Input Bus ...

Page 66

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AE16 STS1TXA_2_D7 I TXHDLCDAT_2_7 TXAISEN_2 RECEIVE SYSTEM SIDE INTERFACE PINS TYPE DESCRIPTION TTL Transmit STS-1 Telecom Bus Interface - Channel 2 ...

Page 67

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O B15 RxOH_0 O C23 RxOH_1 AG13 RxOH_2 C15 RxOHENABLE_0 O D21 RxOHENABLE_1 AF13 RxOHENABLE_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive Overhead Data ...

Page 68

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D15 RxOHCLK_0 O E20 RxOHCLK_1 AE13 RxOHCLK_2 E15 RxOHFRAME_0 O D22 RxOHFRAME_1 AD13 RxOHFRAME_2 Y26 RxPERR O AB27 RxPEOP O AA26 ...

Page 69

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O U23 RxUDATA_0 O RxPDATA_0 W26 RxUDATA_1 RxPDATA_1 U24 RxUDATA_2 RxPDATA_2 AA27 RxUDATA_3 RxPDATA_3 Y27 RxUDATA_4 RxPDATA_4 U25 RxUDATA_5 RxPDATA_5 V26 RxUDATA_6 RxPDATA_6 W27 RxUDATA_7 RxPDATA_7 T23 ...

Page 70

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O N27 RXUCLK/RXPCLK I A16 EXTLOS_0 I J23 EXTLOS_1 AC13 EXTLOS_2 A14D RxOOF_0RxOOF_1R O 20AE xOOF_2 14 A15B RxLOS_0RxLOS_1R O 24AG xLOS_2 ...

Page 71

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O STS-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION A21 STS1RXD_CK_0 O RXVALIDFCS_0 RXGFCCLK_0 H24 STS1RXD_CK_1 O RXVALIDFCS_1 RXGFCCLK_1 TxP_STPA 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION ...

Page 72

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG8 STS1RXD_CK_2 O RXVALIDFCS_2 RXGFCCLK_2 A20 STS1RXD_PL_0 O RXIDLE_0 RXLCD_0 D26 STS1RXD_PL_1 RXIDLE_1 RXLCD_1 AE11 STS1RXD_PL_2 RXIDLE_2 RXLCD_2 TYPE DESCRIPTION CMOS ...

Page 73

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C17 STS1RXD_C1J1_0 O TXDS3LINECLK_0 E25 STS1RXD_C1J1_1 TXDS3LINECLK_1 AF10 STS1RXD_C1J1_2 TXDS3LINECLK_2 B18 STS1RXD_DP_0 O TXDS3POS_0 G24 STS1RXD_DP_1 TXDS3POS_1 AG9 STS1RXD_DP_2 TXDS3POS_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC ...

Page 74

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A19 STS1RXD_ALARM_0 O TXDS3NEG_0 H23 STS1RXD_ALARM_1 TXDS3NEG_1/ AB12 STS1RXD_ALARM_2 TXDS3NEG_2 F16 STS1RXD_D0_0 O RXHDLCDAT_0_0 RXGFCMSB_0 E16 STS1RXD_D1_0 O RXHDLCDAT_1_0 RXGFC_0 TYPE ...

Page 75

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O D16 STS1RXD_D2_0 O RXHDLCDAT_2_0 RXCELLRXED_0 B17 STS1RXD_D3_0 OO IO RXHDLCDAT_3_0 O SSE_CLK C16 STS1RXD_D4_0 O RXHDLCDAT_4_0 RXOHIND_0 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS ...

Page 76

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O A18 STS1RXD_D5_0 O RXHDLCDAT_5_0 RXDS3FP_0 B16 STS1RXD_D6_0 O RXHDLCDAT_6_0 RXDS3DATA_0 A17 STS1RXD_D7_0 O RXHDLCDAT_7_0 RXDS3CLK_0 TYPE DESCRIPTION CMOS Receive STS-1 Telecom ...

Page 77

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O F24 STS1RXD_D0_1 O RXHDLCDAT_0_1 RXGFCMSB_1 H22 STS1RXD_D1_1 O RXHDLCDAT_1_1 RXGFC_1 D25 STS1RXD_D2_1 O RXHDLCDAT_2_1 RXCELLRXED_1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive STS-1 ...

Page 78

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O G23 STS1RXD_D3_1 OO IO RXHDLCDAT_3_1 O SSE_POS D23 STS1RXD_D4_1RXH O DLCDAT_4_1RXOHI ND_1 E21 STS1RXD_D5_1RXH O DLCDAT_5_1RXDS3 FP_1 TYPE DESCRIPTION CMOS Receive ...

Page 79

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O C24 STS1RXD_D6_1RXH O DLCDAT_6_1RXDS3 DATA_1 F20 STS1RXD_D7_1 O RXHDLCDAT_7_1 RXDS3CLK_1 AC12 STS1RXD_D0_2 O RXHDLCDAT_0_2 RXGFCMSB_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive STS-1 ...

Page 80

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AD12 STS1RXD_D1_2 O RXHDLCDAT_1_2 RXGFC_2 AF11 STS1RXD_D2_2RXH O DLCDAT_2_2 RXCELLRXED_2 AE12 STS1RXD_D3_2 OO IO RXHDLCDAT_3_2 O SSE_NEG TYPE DESCRIPTION CMOS Receive ...

Page 81

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG10 STS1RXD_D4_2RXH O DLCDAT_4_2RXOHI ND_2 AF12 STS1RXD_D5_2RXH O DLCDAT_5_2RXDS3 FP_2 AG11 STS1RXD_D6_2RXH O DLCDAT_6_2RXDS3 DATA_2 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive STS-1 ...

Page 82

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG12 STS1RXD_D7_2 O RXHDLCDAT_7_2 RXDS3CLK_2 RECEIVE TRANSPORT OVERHEAD INTERFACE AD5 RxTOHClk O AC7 RxTOHValid O AE4 RxTOH O TYPE DESCRIPTION CMOS ...

Page 83

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AB8 RxTOHFrame O AD7 RxLDCCVAL O AE5 RxLDCC O AD8 RxE1F1E2FP O 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive TOH Output Port - ...

Page 84

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AC9 RxE1F1E2 O AC8 RxSDCC O TYPE DESCRIPTION CMOS Receive - Order-Wire Output Port - Output Pin: This output pin, along ...

Page 85

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AD6 RxSDCCVAL O AF4 RxE1F1E2VAL O AE6 RXPOH O 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION CMOS Receive - Section DCC Output Port - DCC ...

Page 86

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AG4 RXPOHCLK O AE7 RXPOHFRAME O AD9 RXPOHVALID O AF5 RxPOH_0 O AG5 RxPOH_1 AF8 RxPOH_2 AE8 RxPOHClk_0 O AE9 RxPOHClk_1 ...

Page 87

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O AF6A RxPOHFrame_0 O D10A RxPOHFrame_1 E10 RxPOHFrame_2 AC10 RxPOHValid_0 O AF7A RxPOHValid_1 C11 RxPOHValid_2 AD11 LOF O AF9 SEF O AG7 LOS O 3-CHANNEL DS3/E3/STS-1 TO ...

Page 88

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O W25 GPI0_0 I/O AC27 GPI0_1 V23 GPI0_2 AB26 GPI0_3 Y25 GPI0_4 AC26 GPI0_5 W24 GPI0_6 AA25 GPI0_7 E7 REFCLK34 I D5 ...

Page 89

... External Redundant Loop Capacitor for Receive PLL: OG This pin connects to the positive side of the external capacitor, which is used to minimize jitter peaking. ANA- External Redundant Loop Capacitor for Receive PLL: LOG This pin connects to the negative side of the external capacitor, which is used to minimize jitter peaking. MISCELLANEOUS PINS 89 XRT94L31 ...

Page 90

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O H5 REFSEL_L I K4 SFM I J3 Test Mode I G2 FL_TSTCLK O J2 ANALOG O N1 VDCTST1 O N2 VDCTST2 ...

Page 91

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O V3 N/C AB1 N/C AA2 N/C AC1 N/C R1 N/C AB2 N/C AC2 N/C T1 N/C AC4 N/C AB5 N/C AD4 N/C AC5 N/C AB7 N/C ...

Page 92

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O N23 Analog VDD Pins _ N2 5V5 H 2L2 TYPE DESCRIPTION 92 REV. 1.0.1 ...

Page 93

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O U3 Digital VDD AE1 AE2 AF3 AB9 AB10 AB11 AB17 AB18 AB19 AF25 AE26 W22 V22 U22 L22 ...

Page 94

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O G6 Digital Ground AF1 AF2 AA6 AB6 AE3 AG1 AG2 AB13 AB14 AB15 AG26 AF26 AB22 AA22 AE25 ...

Page 95

REV. 1.0.1 PIN DESCRIPTION OF THE XRT94L31 (REV. B) PIN # SIGNAL NAME I/O V6 Analog Ground L6 T4 N24 N26 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC TYPE DESCRIPTION 95 XRT94L31 ...

Page 96

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC 1.0 ELECTRICAL CHARACTERISTIC INFORMATION FOR THE XRT94L31 DEVICE 1.1 DC ELECTRICAL CHARACTERISTIC INFORMATION ABLE HARACTERISTIC PPLIES TO ALL S P YMBOL ARAMETER VDDQ I/O Supply Voltage VIH High-Level ...

Page 97

REV. 1.0 IGURE SYNCHRONOUS ODE CS ALE_AS A[6:0] D[7:0] RD_DS WR_R The values for t0 through t7, within this figure can be found in OTE ...

Page 98

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER ABLE IMING NFORMATION FOR THE T D IMING ESCRIPTION t0 Address setup time to pALE low t1 Address hold time from pALE low t2 pRD_L, pWR_L pulse width t3 ...

Page 99

REV. 1.0 IGURE SYNCHRONOUS ODE CS ALE_AS A[6:0] D[7:0] RD_DS WR_R/W RDY_DTACK N : The values for t0 through t7 can be found in OTE ABLE IMING NFORMATION FOR ...

Page 100

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC 1.2.3 MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE IBM P IGURE YNCHRONOUS ODE pCLK pCS_L pRW_L pA[7:0] pD[7:0] pWE_L pOE_L pRdy N : The value ...

Page 101

REV. 1.0 IBM P IGURE YNCHRONOUS ODE pCLK pCS_L pRW_L pA[7:0] pD[7:0] pWE_L pOE_L pRdy N : The value for t0 through t12 can be found in OTE 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC ...

Page 102

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER ABLE IMING NFORMATION FOR THE T D IMING ESCRIPTION t0 pCS_L low to PCLK high t1 pRW_L low to PCLK high t2 Address setup time to PCLK high t3 ...

Page 103

REV. 1.0.1 1.2.4 MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE IDT3051/52 I IGURE YCHRONOUS ODE pCLK pCS_L pALE pA[7:0] pD[7:0] pRdy_L pRD_L pWR_L pDBEN_L N : The values for t0 through t11 can be found ...

Page 104

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IDT3051/52 I IGURE YCHRONOUS ODE pCLK pCS_L pALE pA[7:0] pD[7:0] pRdy_L pRD_L pWR_L pDBEN_L N : The values for t0 through t11 can be found in OTE ...

Page 105

REV. 1.0 ABLE IMING NFORMATION FOR THE T D IMING ESCRIPTION t10 Clock high to pRD_L high t11 Clock high to pDBEN_L high N : Test Conditions 25°C, VCC = 3.3V±5% and 2.5V±5%, unless ...

Page 106

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC F 11. MPC860 IGURE ODE IMING T0 PCLK CS* R/W* T2 A[14:0] D[7:0] WE* OE* TA The value for t0 through t9 can be found in OTE T ...

Page 107

REV. 1.0.1 1.3 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION 1.3.1 STS-3/STM-1 Telecom Bus Interface Timing Information This section presents the timing requirements for the STS-3/STM-1 Telecom Bus Interface. In particular this section prsents the following. 1. Identifies which edge of ...

Page 108

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE N LLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE T A_CLK T X OUTPUT PIN WITHIN THE TxA_CLK REFCLK TxSBFP TxA_D[7:0] Data N : The value for t4, t5, ...

Page 109

REV. 1.0 IGURE N LLUSTRATION OF THE STM ELECOM US NTERFACE t2 RxD_CLK RxD_PL RxD_C1J1 RxD_D[7: The value for t2 and t3 can be found in OTE T 9: ...

Page 110

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE N LLUSTRATION OF THE STM-1 PECL I NTERFACE RxL_CLKL_p RxL_CLKL_n RxL_Data_p RxL_Data_n Table presents information on the Timing parameters for the Receive STS-3/STM-1 PECL Interface ...

Page 111

REV. 1.0 IGURE N LLUSTRATION OF THE E3/STS-1 LIU NTERFACE IN THE NGRESS DS3/E3/STS_1_DATA_IN DS3/E3/STS_1_NEG_IN DS3/E3/STS_1_CLOCK_IN N : The values for t9 and t10 are presented in OTE 1.3.4 Ingress Timing for DS3/E3 ...

Page 112

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC 1.3.5 Ingress Timing for STS-1/STM-0 Applications Table 13 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH ...

Page 113

REV. 1.0 IGURE N LLUSTRATION OF THE DS3/E3/STS-1 LIU I ( NTERFACE IN THE DS3/E3/STS_1_DATA_OUT DS3/E3/STS_1_NEG_OUT DS3/E3/STS_1_CLOCK_OUT N : The value for t11 is presented in OTE 1.3.7 Egress Timing for DS3/E3 Applications Table 15 presents ...

Page 114

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER ABLE IMING NFORMATION FOR THE A A PPLICATIONS PPLICATIONS S YMBOL t11 Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT output delay 1.3.9 Egress Timing for STS-1/STM-0 Applications (Continued) Table 18 ...

Page 115

REV. 1.0.1 Figure 18 presents an illustration of the waveforms of the signals that will be output via the Receive STS-1/ STM-0 Telecom Bus Interface along with the timing parameter (t12 IGURE N LLUSTRATION OF THE ...

Page 116

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE N LLUSTRATION OF THE STM ELECOM US NTERFACE FOR t12 RxD_CLK RxD_PL RxD_C1J1 RxD_D[7:0] A2 Table 20 presents information on the Timing Parameters for ...

Page 117

REV. 1.0 IGURE N LLUSTRATION OF THE STM ELECOM US NTERFACE t13 TxA_CLK TxA_PL TxA_C1J1 TxA_D[7:0] A2 t14 N : The value for t13 and t14 can be found in OTE T 21: ...

Page 118

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE N LLUSTRATION OF THE STM ELECOM US NTERFACE ASSOCIATED WITH STM ODE t13 TxA_CLK TxA_PL TxA_C1J1 TxA_D[7:0] A2 t14 N : The value ...

Page 119

REV. 1.0 IGURE LLUSTRATION OF IMING TxTOHClk TxTOHFrame TxTOHEnable TxTOHIns TxTOH N : The values for t15, t16 and t17 can be found in OTE T 23 ABLE IMING NFORMATION FOR THE S YMBOL ...

Page 120

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE LLUSTRATION OF IMING TxPOHClk TxPOHFrame TxPOHEnable TxPOHIns TxPOH N : The values for t18, t19 and t20 can be found in OTE T 24 ABLE IMING ...

Page 121

REV. 1.0 IGURE LLUSTRATION OF THE P ORT TxTOHClk TxE1F1E2Fr TxE1F1E2Enb TxE1F1E2 N : The values for t21 and t22 can be found in OTE T 25 ABLE IMING NFORMATION FOR THE S YMBOL ...

Page 122

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE LLUSTRATION OF THE P ORT TxTOHClk TxSDCCEnb TxSDCC N : The values for t23 and t24 can be found in OTE T 26 ABLE IMING NFORMATION ...

Page 123

REV. 1.0 IGURE LLUSTRATION OF THE TxTOHClk TxLDCCEnb TxLDCC N : The values for t25 and t26 can be found in OTE T 27 ABLE IMING NFORMATION FOR THE S YMBOL t25 Falling edge ...

Page 124

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE LLUSTRATION OF THE RxTOHClk RxTOHFrame RxTOHValid RxTOH N : The values for t27 and t28 can be found in OTE T 28 ABLE IMING NFORMATION FOR ...

Page 125

REV. 1.0 IGURE LLUSTRATION OF THE RxPOHClk RxPOHFrame RxPOHValid RxPOH N : The values for t29 and t30 can be found in OTE T 29 ABLE IMING NFORMATION FOR THE S YMBOL t29 Falling ...

Page 126

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IGURE LLUSTRATION OF THE P ORT RxTOHClk RxE1F1E2Fr RxE1F1E2Val RxE1F1E2 N : The values for t31 and t32 can be found in OTE T 30 ABLE IMING ...

Page 127

REV. 1.0 IGURE LLUSTRATION OF THE RxTOHClk RxSDCCVal RxSDCC N : The values for t34 and t34 can be found in OTE T 31 ABLE IMING NFORMATION FOR THE S YMBOL t33 Falling edge ...

Page 128

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER The values for t35 and t36 can be found in OTE T 32: T ABLE IMING S YMBOL t35 Falling edge of RxTOHClk to rising edge of RxLDCCValid t36 Falling edge ...

Page 129

REV. 1.0.1 PACKAGE OUTLINE DRAWING F 32. 94L31 P O IGURE ACKAGE UTLINE Note: The control dimension is in millimeter. SYMBOL 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC 504 ...

Page 130

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC GENERAL DESCRIPTION ................................................................................................ 1 APPLICATIONS .......................................................................................................................................... 1 FEATURES ................................................................................................................................................. XRT94L31 ............................................................................................................................... 2 IGURE LOCK IAGRAM OF THE ORDERING INFORMATION....................................................................................................................... 2 PIN DESCRIPTION XRT94L31 (R OF THE 1.0 ELECTRICAL ...

Page 131

REV. 1.0.1 1.3.5 INGRESS TIMING FOR STS-1/STM-0 APPLICATIONS............................................................................................ 112 T 13 ABLE IMING NFORMATION FOR THE DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112 T 14 ABLE IMING NFORMATION FOR THE DS3/E3/STS_1_CLOCK_IN) ..................................................................................................................................... 112 1.3.6 THE EGRESS DS3/E3/STS-1 INTERFACE TIMING ................................................................................................. ...

Page 132

XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC 1.13 RECEIVE SECTION DCC EXTRACTION OUTPUT PORT ........................................................................... 126 F 30 IGURE LLUSTRATION OF THE IMING T 31 ABLE IMING NFORMATION FOR THE 1.14 RECEIVE LINE DCC EXTRACTION OUTPUT ...

Page 133

... Added package outline Drawing EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...

Related keywords