XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 53

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
B22
TXHDLCDAT_1_2
TXCELLTXED_1
STS1TXA_1_D2
SIGNAL NAME
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 1 - Data Bus Input
pin number 2/Transmit High-Speed HDLC Controller Input Interface
block - Channel 1 - Input Data Bus - Pin 2:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 2 -
STS1TXA_1_D2:
This input pin along with STS1TXA_1_D[7:3] and STS1TXA_1_D[1:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 1. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_1.
been disabled.
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Transmit High-Speed HDLC
Controller Input Interface block - Channel 1 - Data Bus Input pin # 2
- TxHDLCDAT_1_2:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 1
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
If the XRT94L31 has been configured to operate in the ATM UNI
Mode
- TXCELLTXED_1 (Cell Transmitted - Channel 1)
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
53
DESCRIPTION
XRT94L31