XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 66

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AE16
TXHDLCDAT_2_7
STS1TXA_2_D7
SIGNAL NAME
TXAISEN_2
I/O
I
RECEIVE SYSTEM SIDE INTERFACE PINS
TTL
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 2 - Input Data Bus
pin number 7/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 7/Transmit DS3/E3 AIS
Input Pin - Channel 2:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 7 -
STS1TXA_2_D7:
This input pin along with STS1TXA_2_D[6:0] function as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 2. The
Transmit STS-1 Telecom Bus interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_2.
N
If the STS-1 Telecom Bus (associated with Channel 2) has been dis-
abled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Data Bus Input Pin # 7 -
Channel 2 -TXHDLCDAT_2_7:
In this configuration, this input pin will function as Bit 5 within the Trans-
mit High-Speed HDLC Controller Input Interface block - Input Data Bus
(e.g., the TxHDLCDat_2[7:0] input pins).T
he Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_2). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
If the XRT94L31 is configured to operate in any other mode that
involves the DS3/E3 Framer block
- Transmit DS3/E3 AIS Enable Input - Channel 2 - TXAISEN_2:
This input pin is used to command the Frame Generator block (within
Channel 1) to generate and transmit the DS3/E3 AIS pattern, as
described below.
•
•
If the XRT94L31 is configured to operate in any other mode that
involves the DS3/E3 Framer block - Transmit DS3/E3 AIS Enable
Input - Channel 2 - TXAISEN_2:
N
OTE
OTE
"Low" - Configures the Frame Generator block to NOT generate and
transmit the DS3/E3 AIS Pattern
"High" - Configures the Frame Generator block to generate and
transmit the DS3/E3 AIS Pattern
: This input pin functions as the MSB (Most Significant Bit) of the
: To control the transmission of DS3/E3 AIS via Software, this input
Transmit (Add) Telecom Bus, for Channel 2.
pin must be tied to GND.
66
DESCRIPTION
REV. 1.0.1