MCP4461T-103E/ML Microchip Technology, MCP4461T-103E/ML Datasheet - Page 14

• Manufacturer Part Number: MCP4461T-103E/ML
• Description: IC DGTL POT 257TAPS 10K 20QFN
• Manufacturer: Microchip Technology

Specifications of MCP4461T-103E/ML

• Package / Case: 20-VFQFN Exposed Pad
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 10 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP444X/446X
FIGURE 1-3:
TABLE 1-3:
DS22265A-page 14
I
Note 1:
2
Param.
C AC Characteristics
No.
100
101
2:
3:
4:
5:
6:
7:
SDA
Out
SDA
In
SCL
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
requirement t
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
T
the SCL line is released.
The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V
and V
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
Use Cb in pF for the calculations.
Not Tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
Ensured by the T
R
T
T
Sym
max.+t
HIGH
LOW
IL
I
2
of the falling edge of the SCL signal. This specification is not a part of the I
C BUS DATA REQUIREMENTS (SLAVE MODE)
SU;DAT
I
Characteristic
90
2
Clock high time
Clock low time
C Bus Data Timing.
SU;DAT
103
91
AA
= 1000 + 250 = 1250 ns (according to the standard-mode I
3.4 MHz specification test.
≥ 250 ns must then be met. This will automatically be the case if the device does not
109
2
C-bus device can be used in a standard-mode (100 kHz) I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100
106
109
101
DD
4000
4700
1300
range is described in
Min
600
120
320
160
60
107
–40°C ≤ T
Max
—
—
—
—
—
—
A
≤ +125°C (Extended)
Units
ns
ns
ns
ns
ns
ns
ns
ns
AC/DC characteristics
© 2010 Microchip Technology Inc.
2
C bus specification) before
92
1.8V-5.5V
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
1.8V-5.5V
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
102
2
2
C specification, but
C-bus system, but the
110
Conditions
IH