MCP4461T-103E/ML Microchip Technology, MCP4461T-103E/ML Datasheet - Page 66

• Manufacturer Part Number: MCP4461T-103E/ML
• Description: IC DGTL POT 257TAPS 10K 20QFN
• Manufacturer: Microchip Technology

Specifications of MCP4461T-103E/ML

• Package / Case: 20-VFQFN Exposed Pad
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 10 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP444X/446X
7.5
The Read Command can be issued to both the Volatile
and Nonvolatile memory locations. The format of the
command (see
tion, I
MCP44XX Command Byte, A bit, followed by a
Repeated Start bit, I
“1”), and the MCP44XX transmitting the requested
Data High Byte, and A bit, the Data Low Byte, the
Master generating the A, and Stop condition.
The I
logic one (R/W = 1) to generate a read sequence. The
memory location read will be the last address
contained in a valid write MCP44XX Command Byte or
address 00h if no write operations have occurred since
the device was reset (Power-on Reset or Brown-out
Reset).
During a write cycle (Write or High Voltage Write to a
Nonvolatile memory location) the Read command can
only read the Volatile memory locations. By reading the
Status Register (05h), the Host Controller can
determine when the write cycle has completed (via the
state of the EEWA bit).
Read operations initially include the same address byte
sequence as the write sequence (shown in
This sequence is followed by another control byte
(including the Start condition and Acknowledge) with
the R/W bit equal to a logic one (R/W = 1) to indicate a
read. The MCP44XX will then transmit the data
contained in the addressed register. This is followed by
the master generating an A bit in preparation for more
data, or an A bit followed by a Stop. The sequence is
ended with the master generating a Stop or Restart
condition.
The internal address pointer is maintained. If this
address pointer is for a nonvolatile memory address
and the read control byte addresses the device during
a Nonvolatile Write Cycle (t
with an A bit.
7.5.1
Figure 7-4
For single reads the master sends a STOP or
RESTART condition after the data byte is sent from the
slave.
7.5.1.1
Figure 7-5
Refer to
sequence.
DS22265A-page 66
2
2
C Control Byte requires the R/W bit equal to a
C Control Byte (with R/W bit set to “0”), A bit,
Read Data
Normal and High Voltage
show the waveforms for a single read.
shows the sequence for a Random Reads.
Figure 7-5
SINGLE READ
Random Read
Figure
2
C Control Byte (with R/W bit set to
7-4), includes the Start condi-
for the random byte read
WC
) the device will respond
Figure
6-9).
7.5.2
Continuous reads allows the devices memory to be
read quickly. Continuous reads are possible to all
memory locations. If a nonvolatile memory write cycle
is occurring, then Read commands may only access
the volatile memory locations.
Figure 7-6
reads.
For continuous reads, instead of transmitting a Stop
or Restart condition after the data transfer, the master
reads the next data byte. The sequence ends with the
master Not Acknowledging and then sending a Stop or
Restart.
7.5.3
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. High Voltage commands allow
the device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP44XX’s internal V
7.5.4
The MCP44XX expects to receive complete, valid I
commands and will assume any command not defined
as a valid command is due to a bus corruption and will
enter a passive high condition on the SDA signal. All
signals will be ignored until the next valid Start
condition and Control Byte are received.
shows the sequence for three continuous
CONTINUOUS READS
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
IGNORING AN I
AND “FALLING OFF” THE BUS
DD
© 2010 Microchip Technology Inc.
signal.
2
C TRANSMISSION
2
C