MCP4461T-103E/ML Microchip Technology, MCP4461T-103E/ML Datasheet - Page 55

• Manufacturer Part Number: MCP4461T-103E/ML
• Description: IC DGTL POT 257TAPS 10K 20QFN
• Manufacturer: Microchip Technology

Specifications of MCP4461T-103E/ML

• Package / Case: 20-VFQFN Exposed Pad
• Temperature Coefficient: 150 ppm/°C Typical
• Taps: 257
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Pots: Quad
• Taps Per Pot: 257
• Resistance: 10 KOhms
• Wiper Memory: Non Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 600 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Quad I2C Digital POT with Nonvolatile Memory
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.1.4
The Repeated Start bit (see
current Master Device wishes to continue communicat-
ing with the current Slave Device without releasing the
I
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 6-5:
Waveform.
FIGURE 6-7:
FIGURE 6-8:
© 2010 Microchip Technology Inc.
2
SDA
C bus. The Repeated Start condition is the same as
SCL
SDA
SCL
Note 1: A bus collision during the Repeated Start
SDA
SCL
• SCL goes low before SDA is asserted
• SDA is sampled low when SCL goes
S
condition occurs if:
Repeated Start Bit
low. This may indicate that another
master is attempting to transmit a
data "1".
from low to high.
1st Bit
Condition
Repeat Start Condition
Typical 8-Bit I
I
START
2
C Data States and Bit Sequence.
Figure
2nd Bit 3rd Bit
Sr = Repeated Start
6-5) indicates the
Data allowed
to change
2
C Waveform Format.
1st Bit
4th Bit
Data or
A valid
5th Bit
6.2.1.5
The Stop bit (see
I
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I
devices.
FIGURE 6-6:
Transmit Mode.
6.2.2
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP44XX will not stretch the clock signal (SCL)
since memory read access occur fast enough.
6.2.3
If any part of the I
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
2
SDA A / A
SCL
C Data Transfer Sequence. The Stop bit is defined as
6th Bit
CLOCK STRETCHING
ABORTING A TRANSMISSION
7th Bit
Stop Bit
MCP444X/446X
Figure
2
C transmission does not meet the
8th Bit
Stop Condition Receive or
Condition
2
C interface of all MCP44XX
STOP
6-6) Indicates the end of the
A / A
DS22265A-page 55
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