XC2V8000-4FF1517I Xilinx Inc, XC2V8000-4FF1517I Datasheet - Page 29

• Manufacturer Part Number: XC2V8000-4FF1517I
• Description: IC FPGA VIRTEX-II 1517FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V8000-4FF1517I

• Number Of Labs/clbs: 11648
• Total Ram Bits: 3096576
• Number Of I /o: 1108
• Number Of Gates: 8000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Table 13: Virtex-II Logic Resources Available in All CLBs
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
DS031-2 (v3.5) November 5, 2007
Product Specification
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
R
CLB Array:
112 x 104
Column
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
Row x
16 x 8
8 x 8
Number
10,752
14,336
23,040
33,792
46,592
Slices
1,536
3,072
5,120
7,680
256
512
of
Number
10,240
15,360
21,504
28,672
46,080
67,584
93,184
LUTs
1,024
3,072
6,144
512
of
www.xilinx.com
SelectRAM or Shift
Max Distributed
Register (bits)
1,081,344
1,490,944
163,840
245,760
344,064
458,752
737,280
16,384
49,152
98,304
8,192
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 14: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in
bus widths are identical.
Virtex-II Platform FPGAs: Functional Description
16K x 1 bit
8K x 2 bits
4K x 4 bits
Flip-Flops
Number
Figure
10,240
15,360
21,504
28,672
46,080
67,584
93,184
1,024
3,072
6,144
512
of
29. Input data bus and output data
Carry-Chains
Number
112
144
176
208
96
16
16
32
48
64
80
of
512 x 36 bits
1K x 18 bits
2K x 9 bits
(1)
Module 2 of 4
Chains
Number
of SOP
Table
112
128
160
192
224
16
32
48
64
80
96
(1)
14.
21