XC2V8000-4FF1517I Xilinx Inc, XC2V8000-4FF1517I Datasheet - Page 89

• Manufacturer Part Number: XC2V8000-4FF1517I
• Description: IC FPGA VIRTEX-II 1517FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V8000-4FF1517I

• Number Of Labs/clbs: 11648
• Total Ram Bits: 3096576
• Number Of I /o: 1108
• Number Of Gates: 8000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Source Synchronous Timing Budgets
This section describes how to use the parameters provided in the
develop system-specific timing budgets. The following analysis provides information necessary for determining Virtex-II
contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol Interference
or PCB skew.
Virtex-II Transmitter Data-Valid Window (T
T
source-synchronous data bus at the pins of the device and
is calculated as follows:
Notes:
1. Jitter values and accumulation methodology to be provided in
2. This value depends on the clocking methodology used. See
3. This value represents the worst-case clock-tree skew
4. These values represent the worst-case skew between any two
Revision History
This section records the change history for this module of the data sheet.
DS031-3 (v3.5) November 5, 2007
Product Specification
X
11/07/00
12/06/00
01/15/01
01/25/01
04/23/01
a future release of this document. The absolute period jitter
values found in the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
Note1 for
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
is the minimum aggregate valid data period for a
T
TCKSKEW
Date
X
= Data Period - [Jitter
R
Table
(3)
45.
+ TPKGSKEW
Version
1.0
1.1
1.2
1.3
1.5
DCM Timing Parameters
(1)
•
•
•
•
•
•
Early access draft.
Initial release.
Added values to the tables in the
Switching Characteristics
+ Duty Cycle Distortion
(4)
The data sheet was divided into four modules (per the current style standard).
Updated values in the
Characteristics
Table 18, “Delay Measurement Methodology”
Updated values in the
Characteristics
Added T
Skipped v1.4 to sync with other modules. Reverted to traditional double-column format.
]
REG32
section of the
X
symbol to
tables.
tables.
)
www.xilinx.com
(2)
sections.
+
Virtex-II Performance Characteristics
Virtex-II Performance Characteristics
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table
Virtex-II Receiver Data-Valid Window (R
R
a source-synchronous data bus at the pins of the device
and is calculated as follows:
Notes:
1. This parameter indicates the total sampling error of Virtex-II
2. This value represents the worst-case clock-tree skew
3. These values represent the worst-case skew between any two
Virtex-II Performance Characteristics
X
Source-Synchronous Switching Characteristics
23.
is the required minimum aggregate valid data period for
DDR input registers across voltage, temperature, and process.
The characterization methodology uses the DCM to capture
the DDR input registers’ edges of operation. These
measurements include:
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
R
-
-
-
-
These measurements do not include package or clock tree
skew.
X
= [TSAMP
CLK0 and CLK180 DCM jitter in a quiet system
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
Revision
(1)
+ TCKSKEW
and
and
(2)
Virtex-II Switching
Virtex-II Switching
+ TPKGSKEW
and
Virtex-II
X
Module 3 of 4
)
section to
(3)
]
41