NUC120VE3AN Nuvoton Technology Corporation of America, NUC120VE3AN Datasheet - Page 358
NUC120VE3AN
Manufacturer Part Number
NUC120VE3AN
Description
IC MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120VE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
76
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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NuMicro™ NUC100 Series Technical Reference Manual
TX_NEG
RX_NEG
GO_BUSY
TX_BIT_LEN = 0x01 … 1 bit
TX_BIT_LEN = 0x02 … 2 bits
……
TX_BIT_LEN = 0x1F … 31 bits
TX_BIT_LEN = 0x00 … 32 bits
Transmit At Negative Edge
1 = The transmitted data output signal is changed at the falling edge of SPICLK
0 = The transmitted data output signal is changed at the rising edge of SPICLK
Receive At Negative Edge
1 = The received data input signal is latched at the falling edge of SPICLK
0 = The received data input signal is latched at the rising edge of SPICLK
Go and Busy Status
1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode,
0 = Writing 0 to this bit to stop data transfer if SPI is transferring.
During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit
will be cleared automatically.
Note: All registers should be set before writing 1 to this GO_BUSY bit. When a transfer
is in progress, writing to any register of the SPI/MICROWIRE master/slave core has no
effect.
writing 1 to this bit indicates that the slave is ready to communicate with a master.
- 358 -
Publication Release Date: Dec. 22, 2010
Revision V1.06
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