PK30X256VMD100 Freescale Semiconductor, PK30X256VMD100 Datasheet - Page 57

• Manufacturer Part Number: PK30X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK30X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 102
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.8.7 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Freescale Semiconductor, Inc.
Num
SD5
SD6
SD7
SD8
Num
S1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
2
S switching specifications
Operating voltage
I2S_MCLK cycle time
Description
Symbol
t
t
t
t
THL
THL
THL
OD
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table 39. SDHC switching specifications
Clock fall time
SDHC output delay (output valid)
SDHC input setup time
SDHC input hold time
Description
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 40. I
SD3
SD6
(continued)
Table continues on the next page...
Figure 26. SDHC timing
SD2
SD7
2
S master mode timing
Preliminary
2
SD8
S in master (clocks driven) and slave
SD1
Peripheral operating requirements and behaviors
2 x t
Min.
2.7
SYS
Min.
—
-5
5
0
Max.
3.6
Max.
6.5
—
—
3
Unit
ns
Unit
V
ns
ns
ns
ns
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