HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 98

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
6.4.1.2
Note:
6.4.1.3
6.4.1.4
6.5
Note:
6.5.1
6.5.2
Cortina Systems
TX SPI4-2
After reset or power-up, the TX SPI4-2 interface outputs a constant framing pattern on
TSTAT until it receives the proper SPI4-2 training pattern from the upstream SPI4-2 device.
For more information on the required training pattern, see
Alignment Training Sequence (Data Path De-skew), on page
If TDCLK is applied to the IXF1110 MAC after the device has come out of reset, the system
designer must ensure the TDCLK is stable when applied. Failure to due so can result in the
IXF1110 MAC training on a non-stable clock, causing DIP4 errors and data corruption.
Once the valid training pattern is received and the IXF1110 MAC outputs a 10-port calendar
on TSAT, bit 12 of the
indicates that synchronization on the TX SPI4-2 is complete.
Ports will show a SATISFIED status on the SPI4-2 TSTAT bus until a valid link is established
for that port. To determine if a valid link is established, see
on page
SerDes
After reset or power-up the SerDes interface will start to output idles on the TX_P/N for
forced mode operation. If Auto-Negotiation mode is required bit 5 of the
($ Port_Index + 0x18), on page 129
has received the appropriate code words from the link partner. Refer to
Operation, on page 48
CPU
The CPU interface is ready for operation after power-up or reset. Through this interface, the
user can configure the device for any desired setting from the defaults. (Refer to
Section 5.6, CPU Interface, on page 84
SerDes Power-Down Capabilities
The IXF1110 MAC has the ability to power down the TX and RX SerDes individually on
each port (see
correctly power up and power down the SerDes ports.
These sequences must be followed to ensure a port correctly operates when brought out of
a power-down mode:
Placing the SerDes Port in Power-Down Mode
Bringing the SerDes Port Out of Power-Down Mode
®
1. Disable the port(s) by de-asserting the appropriate bit(s) in the
2. Power-down
3. The SerDes port is now powered down and the TSAT Status for the port is SATISFIED.
1. Power up TX and RX SerDes.
2. Enable the port(s) by de-asserting the appropriate bit(s) in the
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
on page
on page
48.
140.
140.
Section 5.3, SerDes Interface, on page
SerDes TX and RX Power-Down Ports 0-9 ($ 0x787), on page
SPI4-2 RX Calendar ($ 0x702), on page 164
for more information.
must be set. A link is established when the RX SerDes
for more information.)
67). Use the following sequence to
Section 5.2.3, Dynamic Phase
Section 5.1.4, Fiber Operation,
62.
Port Enable ($ 0x500),
Port Enable ($ 0x500),
will be set. This
6.5 SerDes Power-Down
Section 5.1.4, Fiber
Diverse Config
166.
Capabilities
Page 98