EGLXT973QCA3V-873178 Cortina Systems Inc, EGLXT973QCA3V-873178 Datasheet
EGLXT973QCA3V-873178
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Cortina Systems Dual-Port Fast Ethernet PHY Transceiver Datasheet The Cortina Systems (LXT973 Transceiver IEEE 802.3 compliant, dual-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX and 10BASE-T applications. Each port provides a Media Independent Interface (MII) for ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Contents 1.0 Pin Assignments and Signal Descriptions ...............................................................................13 2.0 Signal Descriptions .....................................................................................................................17 3.0 Functional Description................................................................................................................23 3.1 Introduction .........................................................................................................................23 3.1.1 Comprehensive Functionality ................................................................................23 3.2 Interface Descriptions .........................................................................................................23 3.2.1 10/100 Mbps Network Interface ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.10.1 Monitoring Auto-Negotiation ..................................................................................41 3.10.2 Per-Port LED Driver Functions ..............................................................................41 4.0 Application Information ..............................................................................................................42 4.1 Design Recommendations..................................................................................................42 4.1.1 General Design Guidelines ....................................................................................42 4.1.2 Power Supply Filtering ...........................................................................................42 4.1.3 Power and Ground ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 16.0 Mechanical Specifications ..........................................................................................................92 16.1 Top Label Marking ..............................................................................................................92 17.0 Product Ordering Information ....................................................................................................95 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Page 5 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Tables 1 PQFP Pin List ................................................................................................................................14 2 Port 0 Signal Descriptions .............................................................................................................17 3 Port 1 Signal Descriptions .............................................................................................................18 4 Network Interface Signal Descriptions...........................................................................................19 5 Global Control & Configuration Signal Descriptions ......................................................................20 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 49 MDIO Timing Parameters ..............................................................................................................89 50 Power-Up Timing Parameters .......................................................................................................90 51 RESET Pulse Width and Recovery Timing Parameters ................................................................91 52 Product Ordering Information ........................................................................................................95 ® Cortina Systems LXT973 10/100 Mbps Dual-Port ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figures 1 Block Diagram ...............................................................................................................................12 2 Pin Assignments ............................................................................................................................13 3 Interfaces.......................................................................................................................................24 4 Loopback Paths ............................................................................................................................27 5 Management Interface Read Frame Structure ..............................................................................28 6 Management Interface Write Frame Structure ..............................................................................28 7 Port ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Revision History Updated the product top marking diagrams First release of this document from Cortina Systems, Inc. Modified Figure 2, Pin Assignments, on page 13. Added Section 16.1, Top Label Marking, ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Added Figure 15 “Recommended LXT973-to-5 VFiber Transceiver Interface Added Figure 16 “ON Semiconductor* Triple PECL-to-LVPECL Logic Changed PECL to LVPECL in first paragraph, second sentence under Modified table note 2 in ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Added Figure 39 “Power-Up Timing” and Table 50 “Power-Up Timing Added Figure 40 “RESET Pulse Width and Recovery Timing” Parameters” Section A, “Product Ordering Information”: Added product ordering information table and ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 1 Block Diagram RESET Management / Mode Select PWRDN Logic & LED Drivers MDIO MDC Register Set TXDn<3.0> TXENn Parallel/Serial TXERn Converter TXCLKn Mgmt Counters Register Set Clock Generator Port ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 1.0 Pin Assignments and Signal Descriptions Figure 2 Pin Assignments TXD1_2 TXD1_3 COL1 CRS1 AUTO_NEG1 AUTO_NEG0 SD_2P5V/SPEED1 SD_2P5V/SPEED0 DUPLEX1 DUPLEX0 LED_CGF0 LED_CGF1 RESET SGND REFCLK GNDD FIBER_TP1 FIBER_TP0 MDDIS1 MDDIS0 PWRDWN1 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 1 PQFP Pin List (Sheet Pin Signal Names 1 TXD1_2 2 TXD1_3 3 COL1 4 CRS1 5 AUTO_NEG1 6 AUTO_NEG0 7 SD_2P5V/SPEED1 8 SD_2P5V/SPEED0 9 DUPLEX1 10 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 1 PQFP Pin List (Sheet Pin Signal Names 34 RXCLK0 35 RXER0 36 TXER0 37 TXCLK0 38 TXEN0 39 TXD0_0 40 VCCD 41 GNDD 42 TXD0_1 43 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 1 PQFP Pin List (Sheet Pin Signal Names 68 DPBN_1 69 GNDR 70 GNDT 71 DPAP_1 72 DPAN_1 73 VCCR 74 VCCPECL 75 SD1 76 SD0 77 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 2.0 Signal Descriptions Table 2 Port 0 Signal Descriptions (Sheet Pin # Signal Names 44 TXD0_3 43 TXD0_2 42 TXD0_1 39 TXD0_0 38 TXEN0 36 TXER0 37 TXCLK0 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 2 Port 0 Signal Descriptions (Sheet Pin # Signal Names 20 MDDIS0 26 MDC0 25 MDIO0 Analog Input Analog Output ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 3 Port 1 Signal Descriptions (Sheet Pin # Signal Names 3 COL1 4 CRS1 19 MDDIS1 22 MDC1 23 MDIO1 Analog Input ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 4 Network Interface Signal Descriptions (Sheet Signal TP Pin # Names Op 67 DPBP_1 TX+ 68 DPBN_1 TX- 71 DPAP_1 RX+ 72 DPAN_1 RX- 75 SD1 – ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 6 Power Supply Signal Descriptions Pin # Signal Names 40, 91 VCCD 27, 47, VCCIO 84 VCCPECL 58, 73 VCCR 65, 66 VCCT 16, 41, GNDD 90, 28, ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 7 Per Port LED and Configuration Signal Descriptions (Sheet Pin # Signal Names SD_2P5V/ 8 SPEED0 SD_2P5V/ 7 SPEED1 10 DUPLEX0 9 DUPLEX1 18 FIBER_TP0 17 FIBER_TP1 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.0 Functional Description 3.1 Introduction The Cortina Systems (LXT973 Transceiver IEEE-compliant, dual-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX and 10BASE-T applications. The device incorporates full Media ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 3 Interfaces DATA Interface MDIO Management Interface Port LED's Address / Control 3.2.1.1 Twisted-Pair Interface The LXT973 Transceiver supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5, Unshielded Twisted-Pair ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.2.1.2 MDI Crossover (MDIX) The LXT973 Transceiver crossover function, which is compliant to the IEEE 802.3, clause 23 standard, connects the transmit output of the device to the far-end receiver in ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 • For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet. ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Test loopback is available for both 100BASE-TX and 10BASE-T operation and is enabled by setting the following register bits: • Register bit 0. (loopback mode) • Register bit 0.8 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.3.8.1 MII Management Interface The LXT973 Transceiver supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.3.8.2 MII Addressing The MDIO management protocol allows one controller to communicate with multiple LXT973 Transceiver chips. Pins ADDR_<4:1> determine the base address. Each port adds its port number to the ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.4.2 Clock Requirements 3.4.2.1 Reference Clock / External Oscillator The LXT973 Transceiver requires a constant enabled reference clock (REFCLK). REFCLK frequency must be 25 MHz. Considering overall system performance first, the ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.5.3 Power-Down Mode The LXT973 Transceiver incorporates numerous features to maintain the lowest power possible. The device can be put into a low-power state via Register 0 as well as a ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.5.5 Hardware Configuration Settings The LXT973 Transceiver provides a hardware option to set the initial device configuration. The hardware option uses four per-port configuration pins that provide control (see Table 9 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.6 Link Establishment 3.6.1 Auto-Negotiation The LXT973 Transceiver attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 pulse positions spaced 62.5 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.6.1.5 Parallel Detection In parallel with auto-negotiation, the LXT973 Transceiver also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps IDLE symbols. If either is detected, the device automatically ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.7.2 Twisted-Pair Interface When operating at 100 Mbps, the LXT973 Transceiver continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT973 Transceiver generates IDLE symbols. During 10 Mbps operation, ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.7.6 Far End Fault In fiber mode, the SDn pin monitors signal quality. If signal quality degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.8.2 100BASE-X Protocol Sublayer Operations In the seven-layer OSI communications model, the LXT973 Transceiver is a Physical Layer 1 (PHY) device. The LXT973 Transceiver implements the Physical Coding Sublayer (PCS), Physical ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 10 Protocol Sublayers PCS Sublayer PMA Sublayer PMD Sublayer 3.8.4 PMA Sublayer 3.8.4.1 Link Failure Override The LXT973 Transceiver normally transmits 100 Mbps data packets or IDLE symbols only if ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.8.4.4 Scrambler/Descrambler The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.9 10 Mbps Operation The LXT973 Transceiver operates as a standard 10BASE-T transceiver and supports all the standard 10 Mbps functions. During 10BASE-T operation, the LXT973 Transceiver transmits and receives Manchester-encoded ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 3.10 Monitoring Operations 3.10.1 Monitoring Auto-Negotiation Auto-negotiation may be monitored as follows: • Link Status Register bit 1 once the link is established. • Additional bits in Register 1 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 4.0 Application Information 4.1 Design Recommendations The LXT973 Transceiver is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT973 Transceiver. The analog section supplies ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 4.1.5 The Fiber Interface The fiber interface consists of an LVPECL transmit and receive pair to an external fiber- optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 4.1.6 Twisted-Pair Interface Use the following standard guidelines for a twisted-pair interface: • Place the magnetics as close as possible to the LXT973 Transceiver. • Keep transmit pair traces as short ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 4.2 Typical Application Circuits Figure 12 through Figure 17 on page 50 LXT973 Transceiver. Figure 12 Power and Ground Supply Connections SGND GNDR/GNDT VCCR/VCCT LXT973 VCCD GNDD VCCIO VCCPECL GNDPECL ® ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 13 Typical Twisted-Pair Interface Port 0 LXT973 Port 1 LXT973 1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT973 Transceiver. 2. The 100 Ω ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 14 Recommended LXT973 Transceiver Transceiver-to-3.3 V Fiber Transceiver Interface Circuitry +2.5 V DPBNn DPBPn LXT973 SDn DPANn DPAPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 15 Recommended LXT973 Transceiver-to-5 V Fiber Transceiver Interface Circuitry +2.5 V DPBNn DPBPn LXT973 SDn DPANn DPAPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 16 ON Semiconductor* Triple PECL-to-LVPECL Logic Translator 0.01 μ Ω PECL Input Signal 130 Ω Fiber Txcvr) Figure 17 Typical MII Interface MAC ® Cortina ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 4.3 Initialization At power-up or reset, the LXT973 Transceiver performs the initialization as shown in Figure 18 on page 52. When the MDDISn pin is High, the LXT973 Transceiver enters Manual ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 18 Initialization Sequence Table 12 Mode Control Settings MDDISn Low High - - ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Power-up or Reset Read H/W Control ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 5.0 Configuration When the LXT973 Transceiver is first powered on, reset, or encounters a link-down state, it must determine the line speed and operating conditions to use for the network link. ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 13 Configuration Settings (Hardware Control Interface) (Sheet FIBER_TPn AUTO_NEGx High Low High Low High Low 1. These pins also set the default values for Registers 0 and ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 6.0 Auto Negotiation The LXT973 Transceiver PHY supports the IEEE 802.3u auto-negotiation scheme with Next Page capability. Next Page exchange utilizes Register 7 to send information and Register 8 to receive ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 7.0 Auto-MDI/MDIX Twisted-pair Ethernet PHYs must be correctly configured for MDI or MDIX operation to inter operate. This has historically been accomplished using special patch cables, magnetics pinouts, or PCB wiring. ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 8.0 100 Mbps Operation The MAC passes data to the LXT973 Transceiver over the MII. The LXT973 Transceiver encodes and scrambles the data, then transmits it using MLT-3 (for 100BASE-TX-over- copper), ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 8.1.1 Scrambler Seeding Once the transmit data (or IDLE symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 22 100BASE-TX Reception with Invalid Symbol RXCLK RXDV RXD<3:0> preamble SFD SFD DA RXER Figure 23 100BASE-TX Transmission with no Errors TXCLK TXEN TXD<3:0> P CRS COL Figure 24 100BASE-TX ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 9.0 Fiber Interface The fiber ports of the LXT973 Transceiver are designed to connect to common industry standard fiber modules. The fiber ports incorporate LVPECL receivers and drivers, allowing for seamless ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 10.0 10 Mbps Operation The LXT973 Transceiver operates as a standard 10 Mbps transceiver. Data transmitted by the MAC as a 4-bit nibble is serialized, Manchester-encoded, and transmitted on the twisted-pair ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 10.6 Dribble Bits The LXT973 Transceiver device handles dribbles bits. If one to four dribble bits are received, the nibble is passed across the interface. The data passed across is padded ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 11.0 Clock Generation 11.1 External Oscillator Figure 25 through Figure 27 on page 64 10BASE-T and 100BASE-TX in the LXT973 Transceiver. Figure 25 MII 10BASE-T DTE Mode Auto-Negotiation TXCLK ( Sourced ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 27 Link Down Clock Transition RXCLK TXCLK ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Link Down condition/Auto Negotiate Link Up Any Clock 2.5 MHz Clock Clock ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 12.0 Register Definitions The LXT973 Transceiver register set includes 16 registers per port. Refer to complete register listing. Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 16 Control Register (Address 0) Bit Name 0.15 RESET 0.14 Loopback Speed Selection 0.13 (LSB) Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 0.8 Duplex Mode 0.7 Collision ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 17 Status Register (Address 1) Bit Name 1.15 100BASE-T4 100BASE-X 1.14 Full- Duplex 100BASE-X 1.13 Half- Duplex 10 Mbps Full- 1.12 Duplex 10 Mbps Half- 1.11 Duplex 100BASE-T2 1.10 Full- ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 18 PHY Identification Register 1 (Address 2) Bit Name 2.15:0 PHY ID Number 1. Refer to Table 15 on page 65 Table 19 PHY Identification Register 2 (Address 3) Bit ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 20 Auto-Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11 Asymmetric Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX 4.8 Full-Duplex 4.7 100BASE-TX ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 21 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved 5.12:11 Asymmetric Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 22 Auto-Negotiation Expansion Register (Address 6) Bit Name 6.15:6 Reserved 6.5 Base Page Parallel Detection 6.4 Fault Link Partner Next 6.3 Page Able 6.2 Next Page Able 6.1 Page Received ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 23 Auto-Negotiation Next Page Transmit Register (Address 7) Bit Name Next Page 7.15 (NP) 7.14 Reserved Message Page 7.13 (MP) Acknowledge 2 7.12 (ACK2) Toggle 7.11 (T) Message/Unformatted 7.10:0 Code ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 25 Port Configuration Register (Address 16) Bit Name 16.15 Reserved 16.14 Link Test Disable 16.13 Transmit Disable Bypass Scramble 16.12 (100BASE-TX) Bypass 4B/5B 16.11 (100BASE-TX) Jabber 16.10 (10BASE-T) SQE 16.9 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 26 Special Function Register (Address 27) Bit Name Line Length Indication Line Length 27.15:13 Indicator Special Functions 27.12 Reserved Per-Port Rise 27.11:10 time Control 27.9 Auto MDIX enable 27.8 Auto ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 13.0 Magnetics Information The LXT973 Transceiver requires a 1:1 ratio for both the receive and transmit path. Refer to Table 30 for transformer requirements. Transformers meeting these requirements are available from ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 14.0 Test Specifications Table 28 on page 76 Note: Figure 42 on page 91 Transceiver. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 29 Operating Conditions (Sheet Parameter V Current 100BASE-FX CC Power-Down Mode Auto-Negotiation 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 32 Digital Input/Output Characteristics - MII Pins Parameter Input Low voltage Input High voltage Input Current Output Low voltage Output High voltage 1. Typical values are at 25°C, and are ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 35 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 37 100BASE-FX Transceiver Characteristics Parameter Peak-to-peak differential output voltage Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25°C, and ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 15.0 Timing Diagrams The LXT973 Transceiver device meets all timings for MII per the IEEE 802.3u standard. Figure 29 through Figure 34 on page 86 Figure 29 100BASE-TX Transmit Timing - ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 30 100BASE-TX Receive Timing - 4B Mode Twisted-Pair RXD<3:0> Note: Table 41 MII - 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD<3:0>, RXDV, RXER setup to RXCLK High RXD<3:0>, ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 31 100BASE-FX Transmit Timing TXCLK TXEN TXD<3:0> DPBP/N CRS Table 42 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TXEN, TXER setup to TXCLK High TXD<3:0>, TXEN, TXER hold from TXCLK High ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 32 100BASE-FX Receive Timing DPAP/N CRS RXDV RXD<3:0> RXCLK COL Table 43 100BASE-FX Receive Timing Parameters Parameter RXD<3:0>, RXDV, RXER setup to RXCLK High RXD<3:0>, RXDV, RXER hold from RXCLK ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 33 10BASE-T Transmit Timing (Parallel Mode) TXCLK TXD, TXEN, TXER CRS Twisted-Pair Output Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1. Note: Table 44 MII - 10BASE-T Transmit ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 34 10BASE-T Receive Timing (Parallel Mode) RXCLK RXD, RXDV, RXER CRS Twisted-Pair Input COL Twisted-pair input default pins are as follows: DPBP/N_0 and DPAP/N_1. Note: Table 45 MII - 10BASE-T ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 35 10BASE-T SQE (Heartbeat) Timing TXCLK TXEN COL Table 46 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) delay after TXEN de- asserted COL (SQE) pulse duration 1. Typical values ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 37 Fast Link Pulse Timing Twisted-Pair Output Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1. Note: Figure 38 FLP Burst Timing Twisted-Pair Output Twisted-pair output default pins are ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 39 MDIO Input Timing MDC MDIO Figure 40 MDIO Output Timing MDC MDIO Table 49 MDIO Timing Parameters (Sheet Parameter MDIO setup before MDC 1. Typical values ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Table 49 MDIO Timing Parameters (Sheet Parameter MDIO hold after MDC MDC to MDIO output delay MDC Clock Speed 1. Typical values are at 25°C, and are for ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 42 RESET Pulse Width and Recovery Timing RESET MDIO,etc. Table 51 RESET Pulse Width and Recovery Timing Parameters Parameter RESET pulse width 2 RESET recovery delay 1. Typical values are ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 16.0 Mechanical Specifications Figure 43 Mechanical Specifications Side pin count = 30 pins E Side pin count = 20 pins for sides with even ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 44 Example of Top Marking Information Labeled as Cortina Systems, Inc. AAAOOOAAA AywwX00a Country of Origin Figure 45 Sample PQFP Package (marked as Intel*) – LXT973QC Transceiver Figure 46 shows ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 46 Sample Pb-Free (RoHS-Compliant) PQFP Package (marked as Intel*) – * Intel EGLX973QC Transceiver ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Pin 1 EGLXT973C A3 XXXXXXXX ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 17.0 Product Ordering Information Table 52 lists the LXT973 Transceiver product ordering information. the ordering information matrix. Table 52 Product Ordering Information Number SLXT973QC.A3V EGLXT973QC.A3V SLXT973QE.A3V EGLXT973QE.A3V ® Cortina Systems LXT973 ...
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LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 47 Ordering Information – Sample S LXT 973 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Product Revision Alphanumeric characters Temperature ...
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For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...