S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 121

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2010/05/18
• Place the ferrite beads (L1 and L2) parallel to each other with minimal clearance
• The analog ground point where bypass cap (C2) connects to the ground isolation
• The same star topology rules used for analog ground apply to the analog power connec-
• All of the trace lengths should be as short as possible.
• If possible, have all the PLL traces on the same outside layer of the board. The only
• If possible, include a partial plane under the PLL area only (area under PLL components
• If possible, keep other board signals from running right next to PLL pin vias on any
• Wherever possible use thick traces, especially with the analog ground and power star
It is likely that manufacturing rules will prohibit routing the ground and power star connec-
tions as suggested. For instance, four wide traces converging on a single pad could have
reflow problems during assembly because of the thermal effect of all the copper traces
around the capacitor pad. One solution might be to have only a single trace connecting to
the pad and then have all the other traces connecting to this wide trace a minimum distance
away from the pad. Another solution might be to have the traces connect to the pad, but
with thermal relief around the pad to break up the copper connection. Ultimately the board
must also be manufacturable, so best effort is acceptable.
between them. Both bypass caps (C2 and C3) should be as close as possible to the
inductors. The traces from C3 to the power planes should be short parallel traces on the
same side of the board with just the normal small clearance between them. Any signifi-
cant loop area here will induce noise. If there is a voltage regulator on the board, try to
run these power traces directly to the regulator instead of dropping to the power planes
(still follow above rules about parallel traces).
inductor (L2) becomes the analog ground central point for a ground star topology. None
of the components connect directly to the analog ground pin of the MGE (PLLV
except for a single short trace from C2 to the PLLV
bypass capacitor (C1) should also have a direct connection to the star point.
tion where L2 connects to C2.
exception is C1, which can be put on the other side of the board if necessary. C1 does
not have to be as close to the analog ground and power star points as the other compo-
nents.
and traces). The solid analog plane should be grounded to the C2 (bypass) pad. This
plane won’t help if it is too large. It is strictly an electrostatic shield against coupling
from other layers’ signals in the same board area. If such an analog plane is not possible,
try to have the layer below the PLL components be a digital power plane instead of a
signal layer.
layer.
connections to either side of C2. Try to make them as wide as the component pads – thin
traces are more inductive.
Revision 2.7
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