PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 23

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2
4.2.1
Table 4-2 WRITE TRANSACTION FORWARDING
WRITE TRANSACTIONS
Write transactions are treated as posted write, delayed/split (PCI-X), or immediate write
transactions. Table 4-2 shows the method of forwarding used for each type of write
operation.
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write”, “Memory Write and Invalidate”, and
“Memory Write Block” transactions.
When PI7C21P100B determines that a memory write transaction is to be forwarded across the
bridge, PI7C21P100B asserts DEVSEL# with medium decode timing and TRDY# in the next
cycle, provided that enough buffer space is available in the posted memory write queue for
the address and at least one DWORD of data. Under this condition, PI7C21P100B accepts
write data without obtaining access to the target bus. The PI7C21P100B can accept one
DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The
write data is stored in an internal posted write buffers and is subsequently delivered to the
target. The PI7C21P100B continues to accept write data until one of the following events
occurs:
aligned 4KB boundary, depending on the transaction type.
When one of the last two events occurs, the PI7C21P100B returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C21P100B asserts
its request on the target bus. This can occur while PI7C21P100B is still receiving data on the
initiator bus. When the grant for the target bus is received and the target bus is detected in the
idle condition, PI7C21P100B asserts FRAME# and drives the stored write address out on the
target bus. On the following cycle, PI7C21P100B drives the first DWORD of write data and
continues to transfer write data until all write data corresponding to that transaction is
delivered, or until a target termination is received. As long as write data exists in the queue,
PI7C21P100B can drive one DWORD of write data in each PCI clock cycle; that is, no master
wait states are inserted. If write data is flowing through PI7C21P100B and the initiator stalls,
PI7C21P100B will signal the last data phase for the current transaction at the target bus if the
Type of Transaction
Memory Write
Memory Write and Invalidate
Memory Write Block (PCI-X)
I/O Write
Type 0 Configuration Write
Type 1 Configuration Write
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an
The posted write data buffer fills up.
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Type of Forwarding
Posted
Posted
Posted
Delayed / Split (PCI-X)
Immediate on the primary bus.
Delayed / Split (PCI-X) on the secondary bus.
Delayed / Split (PCI-X)
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B