PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 59

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.47
8.1.48
8.1.49
8.1.50
OPAQUE MEMORY ENABLE REGISTER – OFFSET 70h
OPAQUE MEMORY BASE REGISTER – OFFSET 74h
OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h
OPAQUE MEMORY BASE UPPER 32-BIT REGISTER – OFFSET 78h
BIT
7:1
0
BIT
15:4
3:0
BIT
31:20
19:16
BIT
31:0
FUNCTION
RESERVED
Opaque Memory Enable
FUNCTION
Opaque Memory Base
Address
Address Select
FUNCTION
Opaque Memory Limit
Address
Address Select
FUNCTION
Opaque Memory Base
Upper 32-bit Register
TYPE
TYPE
TYPE
TYPE
RO
RW
RW
RO
RW
RO
RW
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DESCRIPTION
Reserved. Returns 0000000 when read.
Opaque Memory Enable
0: Disable the opaque memory address range if OPAQUE_EN=0.
1: Enable the opaque memory address range if OPAQUE_EN=1.
Reset to the value of OPAQUE_EN during reset.
DESCRIPTION
Opaque Memory Base Address
Address bits[31:20] of the opaque memory base address in
conjunction with the opaque memory base upper 32-bit register and
opaque memory limit address. In this range, memory transactions are
not accepted by PI7C21P100B on both primary and secondary
interfaces.
Reset to 000h
Address Select
Returns 0001 when read to indicate 64-bit addressing.
DESCRIPTION
Opaque Memory Limit Address
Address bits[31:20] of the opaque memory limit address in
conjunction with the opaque memory limit upper 32-bit register and
opaque memory base address. In this range, memory transactions are
not accepted by PI7C21P100B on both primary and secondary
interfaces.
Reset to FFFh
Address Select
Returns 0001 when read to indicate 64-bit addressing.
DESCRIPTION
Opaque Memory Base Upper 32-bit Register
Address bits[63:32] of the opaque memory base address. In this
range, memory transactions are not accepted by PI7C21P100B on
both primary and secondary interfaces.
Reset to FFFF FFFFh
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B