PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 33

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
5.1
5.2
completion message in PCI-X mode. Special cycles received by PI7C21P100B as a target are
ignored.
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C21P100B complies with the ordering rules
set forth in the PCI Local Bus Specification, Revision 2.2 for PCI mode, and PCI-X
Addendum to the PCI Local Bus Specification, Revision 1.0a for PCI-X mode. This chapter
describes the ordering rules that control transaction forwarding across PI7C21P100B.
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those
transactions cross PI7C21P100B.
The following general ordering guidelines govern transactions crossing PI7C21P100B:
ORDERING RULES
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed or split requests is important, the initiator should not start a second
delayed or split transaction until the first one has been completed. If more than one
delayed or split transaction is initiated, the initiator should repeat all retried requests,
using some fairness algorithm. Repeating a delayed or split transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with respect to
write transactions flowing in the other direction. PI7C21P100B can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
The acceptance of a posted memory or memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This is
true for PI7C21P100B and must also be true for other bus agents. Otherwise, a deadlock
can occur.
PI7C21P100B accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C21P100B.
Page 33 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B