PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 47

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.18
8.1.19
8.1.20
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
I/O LIMIT REGISTER – OFFSET 1Ch
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
7:4
3:2
1:0
BIT
15:12
11:10
9:8
BIT
31
30
29
28
27
26:25
24
23
FUNCTION
I/O Base Address
Reserved
32-bit I/O Addressing
FUNCTION
I/O Limit Address
Reserved
32-bit I/O Addressing
FUNCTION
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL# Timing
Data Parity Error
Fast Back-to-Back
Enable
TYPE
RW
TYPE
RO
TYPE
RO
RO
RO
RW
RO
RWC
RWC
RWC
RWC
RWC
RWC
RO
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DESCRIPTION
Specifies the base of the I/O address range bits [15:12] and is used
with the I/O limit register and I/O base upper 16 bits and I/O limit
upper 16-bit registers
Reserved. Returns 00b when read.
Returns 01b when read to indicate PI7C21P100B supports 32-bit I/O
addressing
DESCRIPTION
Address bits[15:12] of the limit address for the address range of I/O
operations that are passed from primary to secondary
Reserved. Returns 00b when read.
Returns 01b when read to indicate PI7C21P100B supports 32-bit I/O
addressing
DESCRIPTION
Detected Parity Error Status
0: Address or data parity error not detected by PI7C21P100B on the
secondary
1: Address or data parity error detected by PI7C21P100B on the
secondary
Reset to 0
Signaled System Error Status
0: PI7C21P100B did not assert SERR# on the secondary
1: PI7C21P100B asserted SERR# on the secondary
Reset to 0
Received Master Abort Status
0: Transaction not terminated with a bus master abort on the
secondary
1: Transaction terminated with a bus master abort on the secondary
Reset to 0
Received Target Abort Status
0: Transaction not terminated with a target abort
1: Transaction terminated with a target abort
Reset to 0
Signaled Target Abort Status
0: Target device did not terminate transaction with a target abort
1: Target device terminated transaction with a target abort
Reset to 0
DEVESEL# Timing Status
01: Medium decoding.
Returns 01h when read.
Data Parity Error Status
0: No data parity error detected on the secondary
1: Data parity error detected on the secondary
Reset to 0
Fast Back-to-Back Status
0: Target not capable of decoding fast back-to-back transactions in
PCI-X mode
1: Target capable of decoding fast back-to-back transactions in
conventional PCI mode
Returns 0 in PCI-X mode and 1 in conventional PCI mode
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B