IES5502T Hendon Semiconductors, IES5502T Datasheet - Page 3

• Manufacturer Part Number: IES5502T
• Description: Buffers & Line Drivers 2.7-5.5V 6.1mA 45ns 400kHz
• Manufacturer: Hendon Semiconductors

Specifications of IES5502T

• Logic Family: IE5502
• Number Of Channels Per Chip: Dual
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 6.1 mA
• Logic Type: Bidirectional Bus Buffer
• Package / Case: SO-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
The ready output (RDY) indicates that the buffer has met
it’s enable conditions, and that communication will now
occur. This is an open-collector transistor which is
switched off when ready, allowing the voltage at the pin to
be pulled high by a pull-up resistor.
6.5
During power-up or live insertion into backplanes, the
IES5502 will start-up in an under voltage lock-out state
(UVLO) where any activity on the input-output ports will be
ignored. This is to ensure that the IES5502 does not try to
operate when there is not enough voltage on the supply.
7
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are specified with respect to pin 4 (GND)
8
All specifications apply over the full operating temperature range of T
Voltages are specified with respect to pin 4 (GND)
2011 Jan 14, Revision 1.5
V
V
V
I
P
T
T
Power supply
V
I
Startup circuitry
UVLO
V
I
V
CC
PRE
SYMBOL
stg
amb
SYMBOL
CC
Sxx-x
EN
tot
CC
PRE
THR
LIMITING VALUES
CHARACTERISTICS
Ready (RDY) - Buffer Connected Indicator
Start-up
Supply voltage range (V
Voltage range (S
Voltage range (EN)
DC current (any pin)
total power dissipation
storage temperature
operating ambient temperature
supply voltage (operating)
supply current (operating)
supply current (stand-by)
under voltage lock-out level
precharge voltage level
precharge current level
logic input threshold voltage
logic output threshold voltage
PARAMETER
PARAMETER
CL-B
, S
CL-C
CC
)
, S
DA-B
V
V
V
V
V
V
V
CC
CC
CC
xxx-B
EN
xxx-B
EN
, S
= V
= 5.5V, V
= V
>1.2V
> 1.2V
DA-C
floating, V
> V
EN
EN
CONDITIONS
)
= 5.5V
PRE
3
, V
EN
Fast Dual Bi-Directional Bus Buffer
CONDITIONS
During this time, the pre-charge circuit will charge all
S
minimise any voltage difference between the ports and
hence minimises disruptions to the bus during hot insertion
into backplanes.
When the supply increases above the UVLO state, the
IES5502 will then monitor the bus for either stop bit or bus
idle condition. When a stop bit condition is detected and
S
a time period of typically 95µS, then the IES5502 will
activate the input-output connection circuitry. The
pre-charge circuitry is switched off. The voltage at the
READY pin is pulled high by an external pull-up resistor to
indicate the input-output connection has been made.
CC
= 0V
CL-B
CL-C
CC
= 3.3V,
= 3.3V,
/S
/S
DA-B
DA-C
amb
= -40°C to +85°C;
backplane ports to a typically 0.73V. This will
are both idle or when all S
with Hot Insertion Logic
−0.3
−0.3
−0.3
−
−
−55
−40
2.7
−
−
−
−
−
−
−
MIN.
MIN.
−
6.1
580
2.2
0.73
20
0.5V
0.5V
TYP.
+7
+16
+16
20
300
+125
+85
CC
CC
MAX.
Product Specification
IES5502
CL
5.5
−
−
−
−
−
−
−
/S
MAX.
DA
V
V
V
mA
mW
°C
°C
ports idle for
UNIT
V
mA
µA
V
V
µA
V
V
UNIT