IES5502T Hendon Semiconductors, IES5502T Datasheet - Page 6

• Manufacturer Part Number: IES5502T
• Description: Buffers & Line Drivers 2.7-5.5V 6.1mA 45ns 400kHz
• Manufacturer: Hendon Semiconductors

Specifications of IES5502T

• Logic Family: IE5502
• Number Of Channels Per Chip: Dual
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 6.1 mA
• Logic Type: Bidirectional Bus Buffer
• Package / Case: SO-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
9.1
Figure 6 shows a typical application for the IES5502. The
IC can level shift between various bus voltages, without
the need for additional external components. Higher bus
voltages and currents outside the range of the standard
I
range capability and higher noise immunity.
The enable pin can be used to interface buses of different
operating frequencies. When enabled, the bus frequency
is limited to the maximum 100 kHz of the slave device.
When disabled, the slave is isolated, and the remaining
bus can be run at 400 kHz. The timing performance and
current sinking capability will allow it to run well in excess
of the 400 kHz maximum limit of the I
Figure 7 shows the IES5502 used in a backplane
application. Peripheral cards and backplanes operating at
a range of voltages can be interfaced together using a
minimum of components. In this example, cards are
running at 1.8 V and 3V, while the backplane is at 5V.
Cards operating buses between 1.8 V and 15 V can be
catered for in the same system.
Each card can be safely isolated from the system by
disabling the IES5502 at the interface to the backplane.
The Hot-Insertion logic on the IES5502 protects against
corrupted or truncated data transmissions on start-up of
buffer operations.
An ideal backplane application for the IES5502 is the
Advanced Telecom Computing Architecture
(AdvancedTCA) as shown in Figure 8. The IES5502 is well
suited to placement on “Field Replaceable Units” (FRUs)
used in either a conventional fully-bused arrangement (not
shown) or in the low cost high noise margin radial
architecture example as shown in Figure 9. It is fully
interoperable with existing systems and components. If
required, Figure 9 shows a simple low-cost circuit for use
at the Shelf Manager for accelerating the rise in bused
systems.
In each of these examples, the buffers are intended to
extend total system capacitance above 400pF, so
anticipate high capacitance on each side. When loading on
one side is small, adding 47pF is suggested to avoid any
waveform ripple, should it occur.
2011 Jan 14, Revision 1.5
2
C bus specification can be catered for, providing a longer
APPLICATION INFORMATION
Design Considerations
2
C fast mode.
6
Fast Dual Bi-Directional Bus Buffer
9.2
The offset voltage between the side acting as the output
(S
IES5502 can be calculated using the relationship:
This calculation is valid for V
point the saturation voltage of the open collector output
drive transistor will begin to affect the characteristic. Input
and output voltages are shown in millivolts, V
supply voltage to the bus) is in volts, and R is in ohms.
An example calculation for VBUS = 3.3V, V
the resistance R pulling up S
S
This can be compared with the offset characteristic shown
in Figure 4.
A2
xx(out)
V
is typically:
Sxx out
V
Input to Output Offset Voltage Calculation
) and the side acting as the input (S
SA2
(
)
=
=
200mV
V
with Hot Insertion Logic
Sxx in
( )
+
=
+
69mV
294mV
69mV
Sxx(in)
A2
is 2k, then the voltage on
+
+
(
≥
Product Specification
3.3 2000
(
IES5502
V
200mV, as below this
BUS
⁄
⁄
R
xx(in)
SA1
) 15 Ω
) 15
BUS
•
•
) of the
= 200mV,
(the
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