APA075-FGG144 Actel, APA075-FGG144 Datasheet - Page 15

• Manufacturer Part Number: APA075-FGG144
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-FGG144

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Array Coordinates
During many place-and-route operations in Actel’s
Designer software tool, it is possible to set constraints
that require array coordinates.
Table 2-2
are measured from the lower left (0,0). They can be used in
region constraints for specific groups of core cells, I/Os, and
RAM blocks. Wild cards are also allowed.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
Table 2-2 •
Figure 2-5 • Core Cell Coordinates for the APA1000
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
is provided as a reference. The array coordinates
Array Coordinates
x
1
1
1
1
1
1
1
(1,169)
(1,167)
(1,165)
(1,164)
Min.
(1,5)
(1,3)
(1,1)
(0,0)
y
1
1
5
5
5
5
5
Logic Tile
128
128
192
224
256
352
96
x
Max.
100
132
164
32
48
68
68
y
Memory
Memory
Blocks
Blocks
Core
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
v5.9
Bottom
y
–
–
cells and core cells. In addition, the I/O coordinate system
changes depending on the die/package combination.
Core cell coordinates start at the lower left corner
(represented as (1,1)) or at (1,5) if memory blocks are
present at the bottom. Memory coordinates use the
same system and are indicated in
coordinates for an APA1000 are illustrated in
For more information on how to use constraints, see the
Designer User’s Guide
software tools.
Memory Rows
(101,101) or (101, 103)
(133,133) or (133, 135)
(165,165) or (165, 167)
(33,33) or (33, 35)
(49,49) or (49, 51)
(69,69) or (69, 71)
(69,69) or (69, 71)
Top
y
or online help for ProASIC
ProASIC
(353,169)
(352,167)
(352,165)
(352,164)
(352,5)
(352,3)
(352,1)
(353,0)
PLUS
Table
Min.
0,0
0,0
0,0
0,0
0,0
0,0
0,0
Flash Family FPGAs
2-2. The memory
All
225, 105
257, 137
353, 169
129, 53
129, 73
193, 73
Figure
97, 37
Max.
PLUS
2-5.
2-5