APA075-FGG144 Actel, APA075-FGG144 Datasheet - Page 83

• Manufacturer Part Number: APA075-FGG144
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-FGG144

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
User Pins
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC
To maintain compatibility with other Actel ProASIC
products, it is recommended that this pin not be
connected to the circuitry on the board.
GL
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
GLMX
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
Actel’s
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
Dedicated Pins
GND
Common ground supply voltage.
V
2.5 V supply voltage.
V
2.5 V or 3.3 V supply voltage.
DD
DDP
Using ProASIC
with
User Input/Output
No Connect
Global Pin
Global Multiplexing Pin
Ground
Logic Array Power Supply Pin
I/O Pad Power Supply Pin
PLUS
standard
Clock Conditioning
LVTTL
and
Circuits).
LVCMOS
PLUS
v5.9
TMS
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
TCK
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 kΩ pull-up resistor to this
pin.
TDI
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO
Serial output for boundary scan. Actel recommends
adding a nominal 20kΩ pull-up resistor to this pin.
TRST
Asynchronous, active low input pin for resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to
Behavior of ProASIC
Special Function Pins
RCK
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
NPECL
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
PPECL
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
Analog V
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
AGND
The analog ground can be connected to the system
ground. For more information, refer to Actel’s
ProASIC
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
PLUS
DD
Using ProASIC
should be V
Clock Conditioning Circuits
Test Mode Select
Test Clock
Test Data In
Test Data Out
Test Reset Input
Running Clock
User Negative Input
User Positive Input
PLL Power Supply
PLL Power Ground
PLUS
DD
Devices
PLUS
ProASIC
(core voltage) 2.5 V (nominal)
Clock Conditioning Circuits
application note.
PLUS
Flash Family FPGAs
application note.
Power-up
Using
2-73