AGL250V5-FGG144 Actel, AGL250V5-FGG144 Datasheet - Page 112

FPGA - Field Programmable Gate Array 250K System Gates

AGL250V5-FGG144

Manufacturer Part Number
AGL250V5-FGG144
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGL250V5-FGG144

Processor Series
AGL250
Core
IP Core
Maximum Operating Frequency
892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGL250V5-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOO DC and Switching Characteristics
Figure 2-24 • Output DDR Timing Diagram
Table 2-166 • Output DDR Propagation Delays
2- 98
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_F
Data_R
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
CLK
CLR
Out
DDOMAX
For specific junction temperature and voltage supply levels, refer to
6
Timing Characteristics
t
Commercial-Case Conditions: T
DDROCLR2Q
1
1.5 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
t
DDROSUD2
J
= 70°C, Worst-Case VCC = 1.425 V
8
Description
3
2
R ev i sio n 1 8
t
DDROHD2
8
Table 2-6 on page 2-7
4
9
3
t
DDRORECCLR
9
10
4
for derating values.
5
TBD
1.07
0.67
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.31
0.28
Std.
10
Units
MHz
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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