AGL250V5-FGG144 Actel, AGL250V5-FGG144 Datasheet - Page 46

FPGA - Field Programmable Gate Array 250K System Gates

AGL250V5-FGG144

Manufacturer Part Number
AGL250V5-FGG144
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGL250V5-FGG144

Processor Series
AGL250
Core
IP Core
Maximum Operating Frequency
892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGL250V5-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOO DC and Switching Characteristics
Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
2- 32
3.3 V
LVTTL /
3.3 V
LVCMOS
3.3 V
LVCMOS
Wide
Range
2.5 V
LVCMOS
1.8 V
LVCMOS
1.5 V
LVCMOS
1.2 V
LVCMOS
1.2 V
LVCMOS
Wide
Range
3.3 V PCI Per PCI
3.3 V
PCI-X
LVDS
LVPECL
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
5. For specific junction temperature and voltage supply levels, refer to
equivalent software default drive strength. These values are for normal ranges only.
connectivity. This resistor is not required during normal operation.
2
3
100 µA 12 mA High
100 µA
12 mA 12 mA High
12 mA 12 mA High
PCI-X
12 mA 12 mA High
12 mA 12 mA High
24 mA
24 mA
2 mA
spec
spec
Commercial-Case Conditions: T
standard)
Applicable to Advanced I/O Banks
Per
2 mA
2 mA
High
High
High
High
High
High
10 25
10 25
5
5
5
5
5
5
5
2
2
1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns
1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns
1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns
1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns
1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
1.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
1.55 2.27 0.25 1.57
1.55 2.24 0.25 1.38
J
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
R ev i sio n 1 8
μ
A drive strength only. The configuration will not operate at the
Table 2-6 on page 2-7
for derating values.
Figure 2-12 on page 2-79
ns
ns
for

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