AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 223

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-153 • Minimum and Maximum DC Input and Output Levels
Figure 2-128 • AC Loading
Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-155 • SSTL 2 Class I
SSTL2 Class I
Drive
Strength
15 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
DOUT
0.66
0.56
0.49
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
3-9.
Min.
–0.3 VREF – 0.2 VREF + 0.2
Timing Characteristics
V
Input High (V)
2.13
1.81
1.59
t
DP
VREF + 0.2
VIL
Max.
V
trip
0.04
0.04
0.03
t
DIN
. See
Table 2-87 on page 2-168
1.33
1.14
1.00
t
PY
Min.
Measuring Point* (V)
V
Test Point
VIH
t
0.43
0.36
0.32
EOUT
1.25
Max.
3.6
V
SSTL2
Class I
25
R e v i s i o n 1
2.17
1.84
1.62
t
Max.
VOL
0.54
ZL
V
J
for a complete table of trip points.
VTT
= 70°C, Worst-Case VCC = 1.425 V,
VCCI – 0.62 15
VREF (typ.) (V)
1.85
1.57
1.38
50
t
30 pF
ZH
VOH
Min.
V
1.25
t
LZ
Actel Fusion Family of Mixed Signal FPGAs
mA mA
I
OL
t
VTT (typ.) (V)
HZ
I
15
OH
1.25
Max.
mA
I
OSL
87
4.40
3.74
3.29
t
ZLS
3
Max.
I
mA
OSH
83
4.08
3.47
3.05
t
ZHS
3
C
Table 3-7 on
LOAD
µA
I
10
IL
30
1
4
Units
(pF)
ns
ns
ns
µA
I
2- 207
10
IH
2
4