AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 229

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-134 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-168 • Minimum and Maximum DC Input and Output Levels
Table 2-169 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-170 • LVPECL
DC Parameter
VCCI
VOL
VOH
VIL, VIH
V
V
V
V
Input Low (V)
1.64
Note:
Speed Grade
Note:
Std.
–1
–2
OUTBUF_LVPECL
ODIFF
OCM
ICM
IDIFF
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 3.0 V
Applicable to Pro I/Os
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
The building blocks of the LVPECL transmitter–receiver are one transmitter macro, one receiver macro,
three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three
driver resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
3-9.
Timing Characteristics
Supply Voltage
Output Low Voltage
Output High Voltage
Input Low, Input High Voltages
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
FPGA
Description
trip
t
. See
DOUT
0.66
0.56
0.49
N
P
Input High (V)
Table 2-87 on page 2-168
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
1.94
2.14
1.82
1.60
t
DP
0.625
1.762
Min.
0.96
1.01
300
1.8
187 W
0
R e v i s i o n 1
3.0
ZO = 50 Ω
ZO = 50 Ω
Measuring Point* (V)
J
Max.
for a complete table of trip points.
1.27
0.97
1.98
2.57
= 70°C, Worst-Case VCC = 1.425 V,
2.11
3.3
Cross point
0.04
0.04
0.03
t
DIN
0.625
1.762
Min.
1.06
1.92
1.01
300
100 Ω
0
Actel Fusion Family of Mixed Signal FPGAs
3.3
Max.
P
N
1.43
2.28
0.97
1.98
2.57
3.6
FPGA
1.63
1.39
1.22
t
PY
0.625
1.762
Min.
+
–
1.30
2.13
1.01
300
0
V
REF
3.6
Max.
(typ.) (V)
INBUF_LVPECL
1.57
2.41
0.97
1.98
2.57
3.9
–
Table 3-7 on
Figure
Units
ns
ns
ns
Units
2-134.
mV
V
V
V
V
V
V
V
2- 213