APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 127

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APA075-PQG208

Manufacturer Part Number
APA075-PQG208
Description
FPGA - Field Programmable Gate Array 75K System Gates
Manufacturer
Actel
Datasheet

Specifications of APA075-PQG208

Processor Series
APA075
Core
IP Core
Maximum Operating Frequency
150 MHz
Number Of Programmable I/os
158
Data Ram Size
27648
Supply Voltage (max)
2.7 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
2.3 V
Number Of Gates
75 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Number
Pin
K10
K11
K12
K13
K14
K15
K16
J12
J13
J14
J15
J16
L10
L11
L12
L13
K1
K2
K3
K4
K5
K6
K7
K8
K9
L1
L2
L3
L4
L5
L6
L7
L8
L9
Function
APA150
PPECL2 /
I/O / GL3
AVDD
Input
V
GND
GND
GND
GND
V
V
GND
GND
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
256-Pin FBGA
Function
APA300
PPECL2 /
I/O / GL3
AVDD
Input
V
V
V
V
GND
GND
GND
GND
GND
GND
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
Function
APA450
I/O / GL3
PPECL2 /
AVDD
Input
V
GND
GND
GND
GND
V
V
GND
GND
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
Function
APA600
PPECL2 /
I/O / GL3
AVDD
Input
V
GND
GND
GND
GND
V
V
GND
GND
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
v5.9
Number
M10
M11
M12
M13
M14
M15
M16
Pin
N10
N11
N12
N13
N14
N15
N16
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
Function
APA150
V
V
V
V
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
256-Pin FBGA
Function
APA300
ProASIC
V
V
V
V
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
PLUS
Function
APA450
V
V
V
V
Flash Family FPGAs
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
Function
APA600
V
V
V
V
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DDP
3-43

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