A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 24

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A3PE1500-FGG676

Manufacturer Part Number
A3PE1500-FGG676
Description
FPGA - Field Programmable Gate Array 1500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3PE1500-FGG676

Processor Series
A3PE1500
Core
IP Core
Maximum Operating Frequency
231 MHz
Number Of Programmable I/os
444
Data Ram Size
276480
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1.5 M
Package / Case
FPBGA-676
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ProASIC3E DC and Switching Characteristics
2- 12
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation
Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation
Component
α
α
Component
β
β
β
1
2
3
1
2
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock
frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1
– Bit 2
– …
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Toggle rate of VersaTile outputs
I/O buffer toggle rate
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
= 50%
= 25%
R e visio n 9
Definition
Definition
Guideline
Guideline
12.5%
12.5%
100%
10%
10%

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