A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 31

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-15 • Summary of AC Measuring Points
Table 2-16 • I/O AC Parameter Definitions
Standard
3.3
LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
LVPECL
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
PYS
HZ
ZH
LZ
ZL
ZHS
ZLS
V
LVTTL
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
/
3.3
V
Input Reference Voltage
(VREF_TYP)
0.75 V
0.75 V
1.25 V
1.25 V
0.8 V
0.8 V
1.0 V
1.0 V
1.5 V
1.5 V
–
–
–
–
–
–
–
–
–
R e v i s i o n 9
Definition
Board Termination
(VTT_REF)
Voltage
1.485 V
1.485 V
0.75 V
0.75 V
1.25 V
1.25 V
1.2 V
1.2 V
1.5 V
1.5 V
–
–
–
–
–
–
–
–
–
ProASIC3E Flash Family FPGAs
Measuring Trip Point
0.615 * VCCI (FF))
0.285 * VCCI (RR)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
Cross point
Cross point
(Vtrip)
0.90 V
0.75 V
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
1.4 V
1.4 V
1.2 V
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