A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 71

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-28 • Output Enable Register Timing Diagram
Table 2-88 • Output Enable Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
Enable
CLK
D_Enable
Preset
EOUT
Clear
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Output Enable Register
Timing Characteristics
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
50%
50%
t
OESUE
1
t
OEHE
50%
t
OESUD
50%
t
OECLKQ
0
t
50%
OEHD
50%
50%
Description
t
J
OEWPRE
= 70°C, Worst-Case VCC = 1.425 V
t
OEPRE2Q
50%
50%
t
50%
OERECPRE
R e v i s i o n 9
50%
t
t
OEWCLR
OECLR2Q
50%
50%
Table 2-6 on page 2-5
t
50%
OERECCLR
50%
t
OECKMPWH
ProASIC3E Flash Family FPGAs
t
OEREMPRE
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.58
0.00 0.00 0.00
0.67 0.76 0.89
0.67 0.76 0.89
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
–2
50%
for derating values.
50%
t
OECKMPWL
–1
Std. Units
t
OEREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 59