A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 55

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-60 • Minimum and Maximum DC Input and Output Levels
Figure 2-15 • AC Loading
Table 2-61 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-62 • HSTL Class I
HSTL Class I
Drive
Strength
8 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
*
Speed
Grade
Std.
–1
–2
Note:
Measuring point = V
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Worst-Case VCCI = .4 V, VREF = 0.75 V
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Timing Characteristics
t
DOUT
0.66
0.56
0.49
Min.
–0.3 VREF – 0.1 VREF + 0.1
V
Input High (V)
trip
VIL
VREF + 0.1
. See
3.18
2.70
2.37
Max.
t
DP
V
Table 2-15 on page 2-19
0.04
0.04
0.03
t
DIN
Min.
Measuring Point*
V
2.12
1.81
1.59
t
VIH
PY
Test Point
0.75
J
(V)
= 70°C, Worst-Case VCC = 1.425 V,
Max.
3.6
V
t
HSTL
Class I
0.43
0.36
0.32
EOUT
for a complete table of trip points.
R e v i s i o n 9
Max.
VOL
0.4
V
VREF (typ.) (V)
V
3.24
2.75
2.42
t
TT
ZL
50
20 pF
VCCI – 0.4
0.75
VOH
Min.
3.14
2.67
2.35
V
t
ZH
Table 2-6 on page 2-5
mA mA
t
I
OL
LZ
8
VTT (typ.) (V)
I
OH
8
t
0.75
HZ
ProASIC3E Flash Family FPGAs
Max.
mA
I
OSL
39
5.47
4.66
4.09
t
1
ZLS
for derating values.
Max.
I
mA
OSH
32
t
5.38
4.58
4.02
ZHS
C
1
LOAD
20
µA
10
I
(pF)
IL
Units
2
ns
ns
ns
µA
2- 43
I
10
IH
2