XC3S1400AN-5FGG484C Xilinx Inc, XC3S1400AN-5FGG484C Datasheet - Page 50

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XC3S1400AN-5FGG484C

Manufacturer Part Number
XC3S1400AN-5FGG484C
Description
IC FPGA SPARTAN-3AN 484FPGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S1400AN-5FGG484C

Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
372
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Chapter 4: Write and Program Commands
50
Table 4-9: Auto Page Rewrite Through Buffer Command Summary
A Low-to-High transition on the CSB input completes the command.
The addressed ISF memory page is then copied into the designated buffer, the memory
page is erased, then the buffer contents are copied back to the addressed page. The
operation is internally self-timed and completes in the Page Erase and Programming time,
T
During the command execution time, the
indicates whether the Auto Page Rewrite operation is in progress or whether it has
completed.
Notes:
1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Auto Page Rewrite Through Buffer command is not supported in simulation.
MOSI
PEP
Pin
Similarly, serially clock in a 24-bit Page Address.
To end the data command, drive CSB High on the falling edge of CLK.
, shown in
Auto Page Rewrite (Buffer 2)
If using the default address scheme, see
If using power-of-2 addressing, see
Auto Page Rewrite (Buffer 1)
Table 4-4
Command
Byte 1
0x58
0x59
and specified in the
www.xilinx.com
(1)
Default Addressing:
See
Power-of-2 Addressing:
See
High Address
READY/BUSY
Spartan-3AN FPGA In-System Flash User Guide
Table A-4, page 89
Table 5-3, page 53
Table A-4, page 89
Spartan-3AN FPGA data
Byte 2
Table 2-2, page 19
24-bit Page Address
Middle Address
bit (bit 7) of the
.
UG333 (v2.1) January 15, 2009
Byte 3
.
sheet.
Status Register
Low Address
Don’t Care
Byte 4
XX
R

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