XC3S1400AN-5FGG484C Xilinx Inc, XC3S1400AN-5FGG484C Datasheet - Page 9

• Manufacturer Part Number: XC3S1400AN-5FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-5FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Accessing In-System Flash Memory After Configuration
Table 1-3: SPI_ACCESS Primitive Attributes
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Attribute
SIM_DEVICE
SIM_USER_ID
SPI_ACCESS Design Primitive
R
Type
String
64-byte
Hex Value
After the FPGA configures, the application loaded into the FPGA can access the ISF
memory using a special design primitive called SPI_ACCESS, shown in
data accesses to and from the ISF memory are performed using an SPI serial protocol.
Neither the Spartan-3AN FPGA itself nor the SPI_ACCESS primitive includes a dedicated
SPI master controller. Instead, the control logic is implemented using the FPGA’s
programmable logic resources. The SPI_ACCESS primitive essentially connects the FPGA
application to the In-System Flash memory array.
Table 1-2
names relating to the logic that drives the data. The FPGA application is always the Master
of each SPI transaction; the ISF memory is always the Slave.
Table 1-2: SPI_ACCESS Primitive Connections
Table 1-3
Port Name
Figure 1-1: SPI_ACCESS Primitive (only available on Spartan-3AN FPGAs)
MISO
MOSI
CLK
CSB
describes the connections to the SPI_ACCESS primitive. The serial data lines are
describes the available attributes for the SPI_ACCESS primitive.
Allowed Values
“3S50AN”,
“3S200AN”,
“3S400AN”,
“3S700AN” or
“3S1400AN”
Any 64-byte hex
value
Direction
Output
Input
Input
Input
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Default
“UNSPECIFIED” Specifies the target device so that the proper
All locations
default to 0xFF
Accessing In-System Flash Memory After Configuration
Master Input, Slave Output. Serial data output from the
ISF memory array back to the FPGA logic.
Master Output, Slave Input. Serial data input to the ISF
memory array from the FPGA logic.
Active-Low chip-enable to ISF memory array, driven by
FPGA logic.
Clock input to ISF memory array, driven by FPGA logic.
MOSI
CSB
CLK
SPI_ACCESS
UG332_C13_06_081506
Description
size SPI Memory is used. This attributes
required to be set.
Specifies the programmed USER ID in the
Security Register
MISO
Function
for the SPI Memory
Figure
1-1. All
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