STM32F107RCT6TR STMicroelectronics, STM32F107RCT6TR Datasheet - Page 61

• Manufacturer Part Number: STM32F107RCT6TR
• Description: IC ARM CORTEX MCU 256KB 64LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F107RCT6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Core: ARM Cortex M3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F105xx, STM32F107xx
5.3.15
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
The STM32F105xx and STM32F107xx I
standard I
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
The I
characteristics
and SCL) .
Table 40.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
to achieve the fast mode I
mode maximum clock 400 kHz.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve standard mode I
2
C communication protocol with the following restrictions: the I/O pins SDA and
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
for more details on the input/output alternate function characteristics (SDA
Parameter
2
C frequencies and it must be a mulitple of 10 MHz in order to reach I
Table
Doc ID 15274 Rev 5
9.
DD
Standard mode I
2
Table
is disabled, but is still present.
C interface meets the requirements of the
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
PCLK1
(3)
40. Refer also to
frequency and V
2
Table 40
C frequencies. It must be higher than 4 MHz
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
Fast mode I
Section 5.3.12: I/O port
Electrical characteristics
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
DD
supply voltage
b
2
C
900
Max
300
300
400
(1)(2)
(3)
2
C fast
61/101
Unit
s
s
pF
µs
ns
µs