MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 13

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

configured so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM
controller. All may exist in the same system. The local bus controller supports the following features:
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The MPC8533E, as a member of the PowerQUICC family and a member of the PowerPC-core-based line
of processors, enjoys an extensive, mature development environment. Freescale's own hardware reference
designs, models, CodeWarrior™ tools, and board support packages are complemented by a wide range of
third party ecosystem offerings, as well as the active engagement of the open source community.
Freescale’s internal Developer Technologies organization enables third parties to offer comparable and
complementary tools and resources.
MPC8533E boasts a development environment which includes:
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Table 1
Freescale Semiconductor
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Revision
Rev. 0
Multiplexed 32-bit address and data bus operating at up to 166 MHz
Eight chip selects support eight external slaves
Up to eight-beat burst transfers
32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Three protocol engines available on a per-chip-select basis
Parity support
Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Supports zero-bus-turnaround (ZBT) RAM
Models and simulators
Board reference designs
Comprehensive software development environments
Debuggers and performance analysis tools
Toolchains
Boot loaders
Operating systems
Board support packages
provides a revision history for this product brief.
Developer Environment
Document Revision History
Location(s)
MPC8533E Integrated Host Processor Product Brief, Rev. 0
This is the first publicly-released version of this document.
Table 1. Revision History
Substantive Change(s)
Developer Environment
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