MCZ33905BS3EK Freescale Semiconductor, MCZ33905BS3EK Datasheet - Page 50

• Manufacturer Part Number: MCZ33905BS3EK
• Description: IC SBC CAN HS 3.3V 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905BS3EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OVERVIEW
occur. The “Safe state” condition is defined by the resistor
connected at the DGB pin. Safe Mode is entered after
additional event or conditions are met: time out for CAN
communication and state at I/O-1 pin.
event: in the safe state, the device can automatically be
awakened by CAN and I/O (if configured as inputs). Upon
Wake-Up, the device operation is resumed: enter in Reset
Mode.
FAIL SAFE FUNCTIONALITY
(i.e. RESET), the Safe Mode can be entered. In this mode,
the SAFE pin is active low.
Description
condition that make the SAFE pin activated have not
recovered, the device can help to reduce ECU consumption,
assuming that the MCU is not able to set the whole ECU in LP
Mode. Two main cases are available:
Mode A
stays ON), until the failure condition recovers (i.e. S/W is able
Exit of Safe Mode
a Wake-Up event: in this safe state the device can
automatically awakened by CAN and I/O (if I/O Wake-Up was
enable by the SPI prior to enter into SAFE Mode). Upon
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FAIL SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
Fail Safe Mode is entered when specific fail conditions
Exiting the safe state is always possible by a Wake-Up
Upon dedicated event or issue detected at a device pin
Exit of the safe state with V
Table 7. Fail Safe Options
Upon activation of the SAFE pin, and if the failure
Upon SAFE activation, the MCU remains powered (V
typically 15 k bits [2,1,0) = [110]: verification enable: resistor at DBG pin is typically
typically 33 k bits [2,1,0) = [101]: verification enable: resistor at DBG pin is typically
typically 68 k bits [2,1,0) = [100]: verification enable: resistor at DBG pin is typically
Resistor at
DBG pin
<6.0 k
bits [2,1,0) = [111]: verification enable: resistor at DBG pin is typically
15 kohm (RB1) - Selection of SAFE Mode B1
68 kohm (RB3) - Selection of SAFE Mode B3
SPI coding - register INIT MISC bits [2,1,0]
33 kohm (RB2 - Selection of SAFE Mode B2
0 kohm (RA) - Selection of SAFE Mode A
(higher priority that Resistor coding)
DD
OFF is always possible by
FAIL SAFE OPERATION
DD
to properly control the device and properly refresh the
watchdog).
Modes B1, B2 and B3
external event, and disable the MCU supply (turn V
The external events monitored are: CAN traffic, I/O-1 low
level or both of them. 3 sub cases exist, B1, B2 and B3.
are no longer active, thus that the car is being parked and
stopped. The I/O low level detection can also indicate that the
vehicle is being shutdown, if the I/O-1 pin is connected for
instance to a switched battery signal (ignition key on/off
signal).
hardware, via the resistor connected at DBG pin, but can be
over written by software, via a specific SPI command.
value at DBG pin (upon transition from INIT to Normal Mode),
and, if no specific SPI command related to Debug resistor
change is send, operates according to the detected resistor.
device behavior, to either confirm or change the hardware
selected behavior. Device will then operate according to the
SAFE Mode configured by the SPI.
Wake-Up, the device operation is resumed, and device
enters in Reset Mode. The SAFE pin remains active, until
there is a proper read and clear of the SPI flags reporting the
SAFE conditions.
Upon SAFE activation, the system continues to monitor
Note: no CAN traffic indicates that the ECU of the vehicle
The selection of the monitored events is done by
By default, after power up the device detect the resistor
The INIT MISC register allow you to verify and change the
Table 7
Safe Mode
code
B1
B2
B3
A
illustrates the complete options available:
Turn OFF 8.0 s after CAN traffic bus idle detection.
Turn OFF 8.0 s after CAN traffic bus idle detection
Turn OFF when I/O-1 low level detected.
AND when I/O-1 low level detected.
Analog Integrated Circuit Device Data
remains ON
V
DD
Freescale Semiconductor
status
DD
OFF).