PCA9601D,118 NXP Semiconductors, PCA9601D,118 Datasheet - Page 4

• Manufacturer Part Number: PCA9601D,118
• Description: IC DUAL BI-DIR BUS BUFFER 8-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9601D,118

• Number Of Channels Per Chip: 2
• Supply Voltage (max): 15 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Interface: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5303-2

NXP Semiconductors
7. Functional description
PCA9601_1
Product data sheet
7.1.1 Fast-mode operation
7.1.2 Fast-mode Plus operation
7.1 Static level offset card side
Refer to
The PCA9601 has two identical buffers allowing buffering of SDA and SCL I
signals. Each buffer is made up of two logic signal paths, a forward path from the I
interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the
buffered bus input, pins RX and RY to drive the I
The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is
identical.
The I
systems.
The logic threshold voltage levels at SX on this I
voltage V
When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal
3 mA with a V
I
SMBus or other systems that use TTL switching levels.
SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of
typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX,
the sink capability of other connected drivers should be taken into account. Most TTL
devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the
requirement to ensure the 0.8 V TTL LOW.
For Fast-mode I
minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C),
which forms part of the external driver loading. When selecting the pull-up it is necessary
to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be
limited (by external drivers) to 2 mA.
When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher
specified sink capability may be used. PCA9601 has a guaranteed sink capability of
15 mA at V
requirement (0.25V
connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be
selected for 15 mA sink current at V
allowed pull-up is (5.5 V − 1 V) / 15 mA = 300 Ω. With 300 Ω pull-up, the Fm+ rise time of
120 ns maximum can be met with total bus loading up to 470 pF.
2
•
•
C-bus specification for all I
sense the voltage state of I
(and TY respectively), and
sense the state of pins RX and RY and pull the I
pin RY is LOW.
2
C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based
Figure 1 “Block diagram of
CC
OL
. The maximum I
OL
= 1 V maximum over 0 °C to 85 °C. That 1 V complies with the bus LOW
All information provided in this document is subject to legal disclaimers.
2
of 0.74 V maximum. That guarantees compliance with the Fast-mode
C-bus operation, the other connected I
bus
) of any Fm+ bus operating at 4 V or greater. Since the other
Rev. 01 — 28 May 2010
2
2
C-bus voltages greater than 3 V, as well as compliance with
C-bus supply voltage is 15 V.
2
C-bus pins SX (and SY) and transmit this state to pin TX
PCA9601”.
OL
= 1 V. For a nominal 5 V bus (5.5 V maximum) the
2
2
C-bus are independent of the IC supply
C-bus interface. These paths:
2
C-bus pin LOW whenever pin RX or
2
C-bus parts may have the
Dual bidirectional bus buffer
PCA9601
© NXP B.V. 2010. All rights reserved.
2
C-bus
2
C-bus
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