HPCS6003C.A0-998952 Cortina Systems Inc, HPCS6003C.A0-998952 Datasheet - Page 2

• Manufacturer Part Number: HPCS6003C.A0-998952
• Description: IC TRANSPORT PROCESSOR 1517-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPCS6003C.A0-998952

• Includes: *
• Function: Optical Transport Processor
• Interface: SFI-4.1, SFI-4.2, SFI-5.1, XAUI, XFI
• Number Of Circuits: *
• Voltage - Supply: 1V, 1.8V, 2.5V
• Current - Supply: *
• Power (watts): *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1017; HPCS6003C.A0-998859

Copyright © 2009 Cortina Systems, Inc.
Forward Error Correction
The 10G Super FEC scheme used in the CS600x
Transport Processor is the Ultr a-Strong FEC (UFEC)
supported by the industry leading Cortina S ystems
IXF30009/IXF30011 Optical Transport Processors and
specified in section I.7 of the ITU G.975.1
recommendation. The device also supports a similar
40G Super FEC scheme according Section I.7
("Ultra-Strong FEC") of the ITU G.975.1
recommendation. The device pro vides 10G & 40G
configurable ultra-FECs with 4%, 7%, 10%, 15%,
20%, and 25% FEC ov erhead rates with a net coding
gain of greater than 10 dB for Ultr a Long Haul (ULH)
and submarine applications. Standard G.709 (RS-255,
239) Forward Error Correction with a net coding gain
of approximately 6 dB, allowing the CS6001 Transport
Processor to be used as a single-chip G.709 FEC
regenerator for 40 Gbps to 40 Gbps, quad 10 Gbps
to/from 40 Gbps or dual 10 Gbps to dual 10 Gbps
applications. FEC capabilities are supplemented with
Advanced Error Rate Monitoring capabilities.
Features
The CS600x Transport Processor supports Core tr ansport
processing for various protocols:
• Full SONET/SDH TOH processing of OC-768 and
• Full G.709 compliant OxU2 and OxU3 o verhead
• Asynchronous aggregation of four independent 10G
• 10GE LAN/WAN, FC-1200, and FC800 non-intrusiv e
• Fully transparent and asynchronous mapping of one
Additional networking features supported include:
• Known pattern (PRBS, constant bit patterns)
• Maintenance signal processing/propagation for
• Reverse multiplexing (40 Gbps to/from 4x10 Gbps) for
• Substantial hardware support for G.709 and G.798
OC-192 signals (termination and gener ation)
termination and generation
class signals into a standard or an o ver-clocked OTU3
Performance Monitoring
40 Gbps or four 10 Gbps tributaries into an O TU3 or
four independent OTU2s
processing on all streams and lay ers
SONET/SDH and OTN
DWDM and cross-connect applications
functions
®
High Speed Interfaces
• The CS600x Transport Processor has two sets of 17
• Four independent 10G class XFI serial interfaces
• Optional DPSK, PSBT (ODB), or DQPSK differential
• 16-bit general purpose microprocessor interface,
Applications
• OTN networks
• FEC regenerators
• 10GE transport solution
• Protocol transparent transport
• Multiservice platforms
• SONET/SDH Add/Drop multiplexers
• Submarine and ULH FEC applications
• 10G/40G core and metro networks
• High density line cards for 10G networks
• 10GE LAN monitoring
Technology
• CS6001/2/3/5: 1517-ball BGA, 40x40 mm
•
• 1.0 V (Core), 1.8 V (Analog), and 2.5 V
• CML, LVDS, and 2.5 V L VCMOS I/Os
x 3.5 Gbps-capable shared high-speed CML or L VDS
configurable I/Os; each set could be configured for
40G or Nx10G (N=1,..,4) class line or client ports
as:
- 40G class SFI-5.1 compliant interface
- 40G class 16-lane client agnostic backplane
- Four independent 10G class backplane or chip-
- Single 10G class 16-bit SFI -4.1 compliant
clocked at up to 12.5 Gbps
pre-coders
Intel*-style and Motorola*-style, synchronous or
asynchronous, interrupt driven or polling mode
(four bi-directional ports)
CS6004: 896-ball BGA, 31x31 mm
(Digital I/Os) operational supplies
interface (extended SFI-4.2)
to-chip interfaces with CML I/Os; each interface
could be configured as a XA UI port or SFI -4.2
interface
parallel interface clocked at up to 800 MHz with
LVDS I/O
2
Product Brief Number: 400967-1.0
2