XC7WH126DC,125 NXP Semiconductors, XC7WH126DC,125 Datasheet
XC7WH126DC,125
Specifications of XC7WH126DC,125
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XC7WH126DC,125 Summary of contents
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XC7WH126 Dual buffer/line driver; 3-state Rev. 01 — 2 September 2009 1. General description The XC7WH126 is a high-speed Si-gate CMOS device. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the ...
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... NXP Semiconductors 4. Marking Table 2. Marking codes Type number XC7WH126DP XC7WH126DC XC7WH126GD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1OE 2OE 7 mna946 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning XC7WH126 1 1OE GND 001aak067 Fig 4. Pin confi ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin 1OE, 2OE GND 4 1Y Functional description [1] Table 4. Function table Control nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V) ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter Conditions t propagation nA to nY; see pd delay enable time nOE to nY; see disable time nOE to nY; see dis power per buffer; ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 6. Input (nA) to output (nY) propagation delays nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 7. Enable and disable times Table 9. Measurement points Type Input ...
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... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Test circuit for measuring switching times Table 10. Test data Type Input ...
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... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 11. Package outline SOT996-2 (XSON8U) ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID XC7WH126_1 XC7WH126_1 Product data sheet Release date ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 14 Abbreviations ...