NX3L4051HR,115 NXP Semiconductors, NX3L4051HR,115 Datasheet
NX3L4051HR,115
Specifications of NX3L4051HR,115
Related parts for NX3L4051HR,115
NX3L4051HR,115 Summary of contents
Page 1
NX3L4051 Single low-ohmic 8-channel analog switch Rev. 3 — 22 December 2010 1. General description The NX3L4051 is a low-ohmic 8-channel analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. The NX3L4051 has three digital select inputs (S1 ...
Page 2
... NXP Semiconductors 3. Applications Cell phone PDA Portable media player Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C NX3L4051HR NX3L4051PW ...
Page 3
... NXP Semiconductors 6. Functional diagram Pin numbers are shown for TSSOP16 package only. Fig 1. Logic symbol NX3L4051 Product data sheet 001aal657 Fig 2. All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 December 2010 NX3L4051 Single low-ohmic 8-channel analog switch 1-OF-8 DECODER ...
Page 4
... NXP Semiconductors 7. Pinning information 7.1 Pinning terminal 1 index area NX3L4051 Transparent top view Fig 3. Pin configuration SOT1039-1 (HXQFN16U) 7.2 Pin description Table 3. Pin description Symbol Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 11, 12, 13, 10, 15 n.c. GND S1, S2 NX3L4051 Product data sheet 001aal659 Fig 4. ...
Page 5
... NXP Semiconductors 8. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level don’t care. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...
Page 6
... NXP Semiconductors 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate [1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0 ...
Page 7
... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions I additional V = GND supply current input Sn and E I capacitance C OFF-state S(OFF) capacitance C ON-state S(ON) capacitance 11.1 Test circuits Fig 5. ...
Page 8
... NXP Semiconductors 11.2 ON resistance [1] Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Symbol Parameter Conditions R ON resistance V = GND to V ON(peak) I (peak R ON resistance V = GND mismatch I SW between V channels resistance V = GND to V ON(flat) I (flatness For NX3L4051PW (TSSOP16 package), all ON resistance values are up to 0.05 higher. ...
Page 9
... NXP Semiconductors 11.3 ON resistance test circuit and graphs Fig 7. Test circuit for measuring ON resistance NX3L4051 Product data sheet GND 001aal663 Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 December 2010 NX3L4051 Single low-ohmic 8-channel analog switch 1.6 ON (Ω) 1 ...
Page 10
... NXP Semiconductors 1 (Ω) 1.2 0.8 0 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 9. ON resistance as a function of input voltage 1 1 (Ω) 0.8 0.6 0.4 0 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = ...
Page 11
... NXP Semiconductors 1 (Ω) 0.8 0.6 0.4 0 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 13. ON resistance as a function of input voltage 3 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see ...
Page 12
... NXP Semiconductors Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Symbol Parameter Conditions t break-before-make see b-m time [1] Typical values are measured at T [2] Break-before-make guaranteed by design. 12.1 Waveform and test circuits Sn, E input output ...
Page 13
... NXP Semiconductors G a. Test circuit b. Input and output measurement points Fig 16. Test circuit for measuring break-before-make timing G Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance External voltage for measuring switching times. EXT V may be connected ...
Page 14
... NXP Semiconductors 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V specified 2.5 ns amb Symbol Parameter THD total harmonic distortion 3 dB frequency f (3dB) response isolation (OFF-state) iso V crosstalk voltage ct Xtalk crosstalk ...
Page 15
... NXP Semiconductors Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 19. Test circuit for measuring the frequency response when channel is in ON-state Adjust f voltage to obtain 0 dBm level at input. i Fig 20. Test circuit for measuring isolation (OFF-state) NX3L4051 Product data sheet Single low-ohmic 8-channel analog switch V 0 ...
Page 16
... NXP Semiconductors a. Test circuit b. Input and output pulse definitions Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch Fig 22. Test circuit for measuring crosstalk between switches NX3L4051 Product data sheet 0.5V 0. logic V I input GND logic input off ...
Page 17
... NXP Semiconductors G a. Test circuit logic input b. Input and output pulse definitions = V C Definition: Q inj O L V = output voltage variation generator resistance. R gen V = generator voltage. gen V may be connected Fig 23. Test circuit for measuring charge injection NX3L4051 Product data sheet off ...
Page 18
... NXP Semiconductors 13. Package outline HXQFN16U: plastic thermal enhanced extremely thin quad flat package; no leads; 16 terminals; UTLP based; body 0.5 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 3.1 mm 0.5 0.00 0.25 2.9 OUTLINE VERSION ...
Page 19
... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 20
... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PDA Personal Digital Assistant 15. Revision history Table 14. Revision history Document ID Release date NX3L4051 v.3 20101222 • Modifications: Section NX3L4051 v ...
Page 21
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 22
... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: NX3L4051 Product data sheet 16 ...
Page 23
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 9 Limiting values Recommended operating conditions Static characteristics 11.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 ...