74AVCH4T245PW,118 NXP Semiconductors, 74AVCH4T245PW,118 Datasheet

TXRX 4BIT TRANSLATING 16TSSOP

74AVCH4T245PW,118

Manufacturer Part Number
74AVCH4T245PW,118
Description
TXRX 4BIT TRANSLATING 16TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AVCH4T245PW,118

Logic Family
74ACH
Number Of Channels Per Chip
2
Propagation Delay Time
6 ns, 12 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Package / Case
TSSOP-16
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5259-2
1. General description
2. Features and benefits
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (V
V
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to V
V
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
GND level, both A and B outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
CC(B)
CC(B)
74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 2 — 3 December 2010
Wide supply voltage range:
Complies with JEDEC standards:
ESD protection:
Maximum data rates:
. A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
V
V
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
380 Mbit/s ( 1.8 V to 3.3 V translation)
CC(A)
CC(B)
: 0.8 V to 3.6 V
: 0.8 V to 3.6 V
CC(A)
CC(A)
and V
and pins nBn are referenced to
CC(B)
CC(A)
). Both V
Product data sheet
or V
OFF
. The I
CC(B)
CC(A)
are at
and
OFF

Related parts for 74AVCH4T245PW,118

74AVCH4T245PW,118 Summary of contents

Page 1

Rev. 2 — 3 December 2010 1. General description The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two ...

Page 2

... NXP Semiconductors  200 Mbit/s ( 1 3.3 V translation)  200 Mbit/s ( 1 2.5 V translation)  200 Mbit/s ( 1 1.8 V translation)  150 Mbit/s ( 1 1.5 V translation)  100 Mbit/s ( 1 1.2 V translation)  Suspend mode  Bus hold on data inputs  ...

Page 3

... NXP Semiconductors 5. Functional diagram V CC(A) 1OE 15 1DIR 2 Pin numbers are shown for SO16, TSSOP16 and DHVQFN16 packages only. Fig 1. Logic symbol Fig 2. Logic diagram (one 2-bit transceiver) 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver; 3-state 1B1 1B2 V CC(B) 1A1 ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AVCH4T245 V 1 CC(A) 2 1DIR 2DIR 3 4 1A1 1A2 5 6 2A1 2A2 7 GND 8 001aak288 Fig 3. Pin configuration SOT109-1 (SO16) 74AVCH4T245 terminal 1 index area 1DIR 2 3 2DIR 4 1A1 5 1A2 2A1 6 GND 2A2 7 Transparent top view (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material ...

Page 5

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT109-1, SOT403-1 and SOT763 CC(A) 1DIR, 2DIR 2, 3 1A1, 1A2 4, 5 2A1, 2A2 6, 7 [1] GND 8, 9 2B2, 2B1 10, 11 1B2, 1B1 12, 13 2OE, 1OE 14 CC(B) [1] All GND pins must be connected to ground (0 V). ...

Page 6

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage A CC(A) V supply voltage B CC(B) I input clamping current IK V input voltage I I output clamping current OK V output voltage ...

Page 7

... NXP Semiconductors 10. Static characteristics Table 7. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I bus hold LOW current BHL I bus hold HIGH current BHH ...

Page 8

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level data input IH input voltage V = 0.8 V CCI 1.95 V CCI 2.7 V CCI 3.6 V CCI nDIR, nOE input V CC(A) V CC(A) V CC(A) V CC(A) V LOW-level ...

Page 9

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output = 100  voltage V CC( mA CC( mA CC( mA CC( mA CC( mA CC(A) I input leakage nDIR, nOE input current CC(A) I bus hold port BHL LOW current V = 0.49 V ...

Page 10

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state port output CC(A) current suspend mode A port CC(B) suspend mode B port 3.6 V CC(B) I power-off A port; V OFF leakage CC(A) current 3.6 V CC(B) B port ...

Page 11

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply A port current V CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(A) B port CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V CC(A) A plus B port ( 0 3.6 V; CC( 0 3.6 V CC(B) A plus B port ( ...

Page 12

... NXP Semiconductors 11. Dynamic characteristics Table 10. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction nAn to PD capacitance nBn); output enabled A port: (direction nAn to nBn); output disabled A port: (direction nBn to nAn); output enabled A port: (direction nBn to nAn) ...

Page 13

... NXP Semiconductors Table 11. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nAn to nBn pd nBn to nAn t disable time nOE to nAn dis nOE to nBn t enable time nOE to nAn en nOE to nBn [ the same as t and t ...

Page 14

... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +85 C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation nAn delay nBn to nAn t disable time nOE to nAn dis nOE to nBn t enable time ...

Page 15

... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +125 C Table 14. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation nAn delay nBn to nAn t disable time nOE to nAn dis nOE to nBn t enable time ...

Page 16

... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...

Page 17

... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance External voltage for measuring switching times. V EXT Fig 9. Test circuit for measuring switching times Table 16. Test data Supply voltage Input [ CC(A) CC( 1.6 V ...

Page 18

... NXP Semiconductors 13. Typical propagation delay characteristics (ns Propagation delay (A to B 0.8 V. CC(B) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 10. Typical propagation delay versus load capacitance; T 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver; 3-state 001aai476 t pd ...

Page 19

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.2 V CC( PLH (ns LOW to HIGH propagation delay ( 1.5 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 11. Typical propagation delay versus load capacitance; T 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver; 3-state ...

Page 20

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.8 V CC( PLH (ns LOW to HIGH propagation delay ( 2.5 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 12. Typical propagation delay versus load capacitance; T 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver; 3-state ...

Page 21

... NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 3.3 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) Fig 13. Typical propagation delay versus load capacitance; T 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver; 3-state 001aai485 t PHL (1) (ns) ...

Page 22

... NXP Semiconductors 14. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 23

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 24

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 25

... NXP Semiconductors XQFN16: plastic, extremely thin quad flat package; no leads; 16 terminals; body 1.80 x 2. terminal 1 index area L terminal 1 index area Dimensions (1) Unit max 0.5 0.05 0.25 mm nom 0.127 0.20 min 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 26

... NXP Semiconductors 15. Abbreviations Table 17. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 18. Revision history Document ID Release date 74AVCH4T245 v.2 20101203 • Modifications: Added type number 74AVCH4T245GU (XQFN16/SOT1161 package). ...

Page 27

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 28

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AVCH4T245 Product data sheet 4-bit dual supply translating transceiver ...

Page 29

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 12 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13 Typical propagation delay characteristics ...

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