MR25H256CDC EverSpin Technologies Inc, MR25H256CDC Datasheet - Page 3

• Manufacturer Part Number: MR25H256CDC
• Description: IC MRAM 256KBIT 40MHZ 8DFN
• Manufacturer: EverSpin Technologies Inc

Specifications of MR25H256CDC

• Format - Memory: RAM
• Memory Type: MRAM (Magnetoresistive RAM)
• Memory Size: 256K (32K x 8)
• Speed: 40MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819-1015

Everspin Technologies © 2010
DEVICE PIN ASSIGNMENT
Signal Name Pin
CS
SO
WP
V
SI
SCK
HOLD
V
SS
DD
1
2
3
4
5
6
7
8
I/O
Input
Output
Input
Supply
Input
Input
Input
Supply
Function
Chip Select
Serial Output
Hold
Ground
Serial Input
Serial Clock
Hold
Power Supply
Figure 1.2 Pin Diagrams (Top View)
WP
V
SO
CS
SS
Table 1.1 Pin Functions
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
A low on the write protect input prevents write operations to the Status
Register.
Power supply ground pin.
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=0). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
Power supply voltage from +2.7 to +3.6 volts.
1
2
3
4
8-Pin DFN
3
8
7
6
5
Document Number: MR25H256 Rev. 2, 4/2010
V
HOLD
SCK
SI
DD
MR25H256