MR25H256CDC EverSpin Technologies Inc, MR25H256CDC Datasheet - Page 6

• Manufacturer Part Number: MR25H256CDC
• Description: IC MRAM 256KBIT 40MHZ 8DFN
• Manufacturer: EverSpin Technologies Inc

Specifications of MR25H256CDC

• Format - Memory: RAM
• Memory Type: MRAM (Magnetoresistive RAM)
• Memory Size: 256K (32K x 8)
• Speed: 40MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819-1015

Everspin Technologies © 2010
SPI COMMUNICATIONS PROTOCOL
Write Status Register (WRSR)
Write Enable (WREN)
Write Disable (WRDI)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 0 by executing a
WREN command while pin WP and bit SRWD correspond to values that make the status register writable
as seen in table 2.2. Status Register bits are non-volatile when the Write Status Register (WRSR) command
is issued immediately following a fresh power-up and WREN command. If the WRSR command is issued
in a different sequence, i.e. not immediately following power-up and WREN, then upon power cycling the
state of the status register bits must be reset before any other part operation.
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The
Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN
command is entered by driving CS low, sending the command code, and then driving CS high.
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 8).
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, send-
ing the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed.
SCK
SCK
CS
SO
SO
SI
CS
SI
Mode 3
Mode 0
Mode 3
Mode 0
0
0
0
0
0
0
Figure 2.2 WREN
1
1
Figure 2.3 WRDI
0
0
High Impedance
High Impedance
2
2
Instruction (06h)
Instruction (04h)
6
0
0
3
3
0
0
4
4
Document Number: MR25H256 Rev. 2, 4/2010
1
1
5
5
1
0
6
6
0
0
7
7
Mode 3
Mode 0
Mode 3
Mode 0
MR25H256