PCF85176H/1,518 NXP Semiconductors, PCF85176H/1,518 Datasheet - Page 14

• Manufacturer Part Number: PCF85176H/1,518
• Description: IC LCD DISPLAY DVR 40SEG 64TQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF85176H/1,518

• Package / Case: 64-TQFP
• Display Type: LCD
• Configuration: 40 Segment
• Interface: I²C
• Current - Supply: 20µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 20
• Number Of Segments: 40
• Maximum Clock Frequency: 2640 Hz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 95 C
• Attached Touch Screen: No
• Maximum Supply Current: 20 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5932-2; PCF85176H/1,518

NXP Semiconductors
PCF85176_1
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
7.9 Backplane outputs
The internal logic of the PCF85176 and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin V
as the clock signal for several PCF85176 in the system that are connected in cascade.
Pin CLK is enabled as an external clock input by connecting pin OSC to V
frame signal frequency is determined by the clock frequency (f
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
The PCF85176 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF85176 in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock:
The display register holds the display data while the corresponding multiplex signals are
generated.
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
•
•
In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
f
fr
=
f
-------
24
clk
All information provided in this document is subject to legal disclaimers.
SS
. If the internal oscillator is used, the output from pin CLK can be used
Rev. 01 — 14 April 2010
Universal LCD driver for low multiplex rates
clk
).
PCF85176
© NXP B.V. 2010. All rights reserved.
DD
. The LCD
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