MC13783VK5 Freescale Semiconductor, MC13783VK5 Datasheet - Page 29

• Manufacturer Part Number: MC13783VK5
• Description: IC PWR MNGMNT ATLAS 3G 247MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC13783VK5

• Applications: Handheld/Mobile Devices
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: *
• Package / Case: 247-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -

4.3.3.2
The stereo DAC incorporates a PLL to generate the proper clocks in master and in slave modes. The PLL
requires an external C//RC loop filter.
In Master Mode, the PLL of the Stereo DAC generates FS and BCL signal based on the reference
frequency applied through one of the CLI inputs. The CLI frequencies supported are 3.6864 MHz, 12
MHz, 13 MHz, 15.36 MHz, 16.8 MHz, 26 MHz and 33.6 MHz. The PLL will also generate its own master
clock MCL used by the stereo DAC itself.
In Slave Mode, FS and BCL are applied to the MC13783 and the MCL is internally generated by the PLL
based on either FS or BCL.
A special mode is foreseen where the PLL is bypassed and CLI can be used as the MCL signal. In this
mode, MCLK must be provided with the exact ratio to FS, depending on the sample rate selected.
In the network mode, it’s possible to select up to 8 time slots (4 time slot pairs).
Freescale Semiconductor
Clock Modes
BCL1
BCL2
CLIB
FS1
FS2
CLIA
STDCCLKSEL
STDCSSISEL
SR3
0
0
0
0
0
0
0
0
Table 15. Stereo DAC Sample Rate Selection SPI Bits
SR2
0
0
0
0
1
1
1
1
Figure 7. Stereo DAC PLL Block Diagram
STDCCLK[3:0]
SR1
0
0
1
1
0
0
1
1
STDCSM=0
STDCSM=0
MC13783 Technical Data, Rev. 3.5
SR0
0
1
0
1
0
1
0
1
MCL
STDCSM=1 &
STDCCLK=101
11025
12000
16000
22050
24000
32000
44100
8000
FS
NFS
NB
NS
1
N
512
512
512
256
256
256
128
128
NR
FS
1
internal master clock MCLint
5644.8k
5644.8k
5644.8k
4096k
6144k
4096k
6144k
4096k
MCL
∅
STDCSM=1 &
STDCCLK=101
N
16
16
16
8
8
8
4
4
B
LPF
NF
1
1411.2k
352.8k
705.6k
1024k
256k
384k
512k
768k
BCL
VCO
Functional Description
NO
1
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