EVB-LAN7500-LC

Manufacturer Part NumberEVB-LAN7500-LC
DescriptionEVALUATION BOARD FOR LAN7500
ManufacturerSMSC
EVB-LAN7500-LC datasheets
 

Specifications of EVB-LAN7500-LC

Design ResourcesEVB-LAN7500-LC BOM EVB-LAN7500-LC Gerber Files EVB-LAN7500-LC SchematicMain PurposeInterface, Ethernet Controller (PHY and MAC)
EmbeddedNoUtilized Ic / PartLAN7500
Primary AttributesUSB 2.0 to 10/100/1000 Ethernet ControllerSecondary AttributesIEEE 802.3, IEEE 802.3u, IEEE 802.3ab Compliant
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names638-1105
EVB-LAN7500
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NUM PINS
NAME
System Reset
1
PME Clear
PME_CLEAR
Detect
VBUS_DET
Upstream
VBUS Power
1
Test
1
Switching
SW_MODE
Regulator
Mode
1
Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad
NUM PINS
NAME
+3.3V Analog
1
Power Supply
Input
+3.3V/+2.5V
VDDVARIO
4
I/O Power
Supply Input
Digital Core
VDD12CORE
6
+1.2V Power
Supply Input
USB PLL
VDD12USBPLL
1
+1.2V Power
Supply Input
Ethernet
+1.2V Port
4
Power Supply
Input For
Channels 0-3
Revision 1.0 (11-01-10)
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Table 2.6 Miscellaneous Pins
BUFFER
SYMBOL
TYPE
nRESET
VIS
This active-low pin allows external hardware to
reset the device.
(PU)
Note:
VIS
This pin may serve as the PME_CLEAR input
when PME mode of operation is in effect. Refer
(PU)
to
Chapter 4, "PME Operation," on page 30
additional information.
IS_5V
Detects state of upstream bus power.
(PD)
For bus powered operation, this pin must be tied
to VDD33A.
For self powered operation, refer to the
LAN7500/LAN7500i reference schematics.
TEST
-
This pin must always be connected to VSS for
proper operation.
VO6
When asserted, this pin places the external
switching regulator into power saving mode.
Note:
BUFFER
SYMBOL
TYPE
VDD33A
P
Refer to
page 36
schematics for connection information.
P
Refer to
page 36
schematics for connection information.
P
Refer to
page 36
schematics for connection information.
P
Refer to
page 36
schematics for additional connection information.
VDD12A
P
Refer to
page 36
schematics for additional connection information.
16
DATASHEET
Datasheet
DESCRIPTION
Assertion of nRESET is required
following power-on.
for
The
SW_MODE_POL
and
SW_MODE_SEL
bits of
Configuration
Flags 1
control the polarity of the pin
and when it is asserted, respectively.
DESCRIPTION
Chapter 6, "Application Diagrams," on
and the LAN7500/LAN7500i reference
Chapter 6, "Application Diagrams," on
and the LAN7500/LAN7500i reference
Chapter 6, "Application Diagrams," on
and the LAN7500/LAN7500i reference
Chapter 6, "Application Diagrams," on
and the LAN7500/LAN7500i reference
Chapter 6, "Application Diagrams," on
and the LAN7500/LAN7500i reference
SMSC LAN7500/LAN7500i