LIS3DHTR STMicroelectronics, LIS3DHTR Datasheet - Page 19

• Manufacturer Part Number: LIS3DHTR
• Description: ACCELEROMETER 3AXIS MEMS 16-LGA
• Manufacturer: STMicroelectronics

Specifications of LIS3DHTR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10613-2

LIS3DH
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
Digital main blocks
FIFO
LIS3DH embeds a 32-slot of 10bit data FIFO for each of the three output channels, X, Y and
Z. This allows a consistent power saving for the system, since the host processor does not
need to continuously poll data from the sensor, but it can wakeup only when needed and
burst the significant data out from the FIFO. This buffer can work accordingly to four different
modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is
selected by the FIFO_MODE bits into the FIFO_CTRL_REG (2E). Programmable
Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated
interrupts on INT1/2 pin (configuration through FIFO_CFG_REG).
Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. As
described in the next figure, for each channel only the first address is used. The remaining
FIFO slots are empty.
FIFO mode
In FIFO mode, data from X, Y and Z channels are stored into the FIFO. A watermark
interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG in order to be raised
when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits of
FIFO_CTRL_REG. The FIFO continues filling until it is full (32 slots of 10data for X, Y and
Z). When full, the FIFO stops collecting data from the input channels.
Stream mode
In the stream mode, data from X, Y and Z measurement are stored into the FIFO. A
watermark interrupt can be enabled and set as in the FIFO mode.The FIFO continues filling
until it’s full (32 slots of 10data for X, Y and Z). When full, the FIFO discards the older data
as the new arrive.
Stream-to-FIFO mode
In Stream-to_FIFO mode, data from X, Y and Z measurement are stored into the FIFO. A
watermark interrupt can be enabled (FIFO_WTMK_EN bit into FIFO_CTRL_REG) in order
to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits
of FIFO_CTRL_REG. The FIFO continues filling until it’s full (32 slots of 10 data for X, Y and
Z). When full, the FIFO discards the older data as the new arrive. Once trigger event occurs,
the FIFO starts operating in FIFO mode.
Retrieve data from FIFO
FIFO data is read through OUT_X (Addr reg 28h,29h), OUT_Y (Addr reg 2Ah,2Bh) and
OUT_Z (Addr reg 2Ch,2Dh). When the FIFO is in stream, Trigger or FIFO mode, a read
operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored into the FIFO.
Each time data is read from the FIFO, the oldest X, Y and Z data are placed into the OUT_X,
OUT_Y and OUT_Z registers and both single read and read_burst operations can be used.
Doc ID 17530 Rev 1
Digital main blocks
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