LIS33DETR STMicroelectronics, LIS33DETR Datasheet

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... ST to produce inertial sensors and actuators in silicon. Table 1. Device summary Order code LIS33DE LIS33DETR April 2009 The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS33DE has dynamically user selectable full scales of ± ...

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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block ...

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LIS33DE 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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LIS33DE List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS 6/ ...

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LIS33DE Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected 2 SCL I C serial ...

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Mechanical and electrical specifications 2 Mechanical and electrical specifications 2.1 Mechanical characteristics T = 25°C unless otherwise noted Table 3. Mechanical characteristics @ Vdd=2.5V Symbol Parameter FS Measurement range Dres Device resolution So Sensitivity Sensitivity change vs TCSO temperature Typical ...

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LIS33DE 2.2 Electrical characteristics T = 25°C unless otherwise noted Table 4. Electrical characteristics @ Vdd=2.5V Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Idd Supply current Current consumption in IddPdn power-down mode Digital high level Input VIH ...

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Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and top. Table 5. SPI slave timing values Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. ...

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LIS33DE 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) ...

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Mechanical and electrical specifications 2.4 Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not ...

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LIS33DE 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of ...

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Functionality 3 Functionality The LIS33DE is an ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...

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LIS33DE 4 Application hints Figure 5. LIS33DE electrical connection Vdd The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed ...

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Digital interfaces 5 Digital interfaces The registers embedded inside the LIS33DE may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are ...

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... LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometers to the same I Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse ...

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Digital interfaces Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave Master ST SAD+W SUB Slave SAK Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred ...

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LIS33DE of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the ...

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Digital interfaces Figure 8. Multiple bytes SPI read protocol (2 bytes example) CS SPC SDI RW MS SDO 5.2.2 SPI write Figure 9. SPI write protocol CS SPC SDI The SPI Write command is performed with 16 clock pulses. Multiple ...

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LIS33DE 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O The SPI read command is ...

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Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 15. Register address map Name Reserved (do not modify) Ctrl_Reg1 Ctrl_Reg2 Ctrl_Reg3 Reserved (do ...

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LIS33DE 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...

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Register description 7.2 CTRL_REG2 (21h) Table 18. CTRL_REG2 (21h) register SIM BOOT 1. Bit to be kept to “0” for correct device functionality. Table 19. CTRL_REG2 (21h) register description SIM SPI serial interface mode selection. Default value: 0 (0: 4-wire ...

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LIS33DE Table 22. Data signal on INT pad control bits (1) ICFG2 These are the allowed bit configurations. Each other configuration may cause incorrect device functionality. 7.4 STATUS_REG (27h) Table 23. STATUS_REG (27h) register ZXYOR ZOR ...

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Register description 7.5 OUT_X (29h) Table 25. OUT_X (29h) register XD7 XD6 X axis output data expressed as 2’s complement number. 7.6 OUT_Y (2Bh) Table 26. OUT_Y (2Bh) register YD7 YD6 Y axis output data expressed as 2’s complement number. ...

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LIS33DE Table 29. FF_WU_CFG (30h) register description (continued) Enable interrupt generation on Y high event. Default value: 0 YHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y ...

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Register description 7.10 FF_WU_THS (32h) Table 32. FF_WU_THS (32h) register DCRM THS6 Table 33. FF_WU_THS (32h) register description DCRM THS6, THS0 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is ...

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LIS33DE 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK ...

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Revision history 9 Revision history Table 36. Document revision history Date 17-Apr-2009 30/31 Revision 1 Initial release Doc ID 15596 Rev 1 LIS33DE Changes ...

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... LIS33DE Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...